timing.cc (6022:410194bb3049) timing.cc (6023:47b4fcb10c11)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 440 unchanged lines hidden (view full) ---

449 _status = DTBWaitResponse;
450 if (split_addr > addr) {
451 RequestPtr req1, req2;
452 assert(!req->isLocked() && !req->isSwap());
453 req->splitOnVaddr(split_addr, req1, req2);
454
455 typedef SplitDataTranslation::WholeTranslationState WholeState;
456 WholeState *state = new WholeState(req1, req2, req,
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 440 unchanged lines hidden (view full) ---

449 _status = DTBWaitResponse;
450 if (split_addr > addr) {
451 RequestPtr req1, req2;
452 assert(!req->isLocked() && !req->isSwap());
453 req->splitOnVaddr(split_addr, req1, req2);
454
455 typedef SplitDataTranslation::WholeTranslationState WholeState;
456 WholeState *state = new WholeState(req1, req2, req,
457 (uint8_t *)(new T), true);
457 (uint8_t *)(new T), BaseTLB::Read);
458 thread->dtb->translateTiming(req1, tc,
458 thread->dtb->translateTiming(req1, tc,
459 new SplitDataTranslation(this, 0, state), false);
459 new SplitDataTranslation(this, 0, state), BaseTLB::Read);
460 thread->dtb->translateTiming(req2, tc,
460 thread->dtb->translateTiming(req2, tc,
461 new SplitDataTranslation(this, 1, state), false);
461 new SplitDataTranslation(this, 1, state), BaseTLB::Read);
462 } else {
462 } else {
463 thread->dtb->translateTiming(req, tc,
464 new DataTranslation(this, (uint8_t *)(new T), NULL, true),
465 false);
463 DataTranslation *translation =
464 new DataTranslation(this, (uint8_t *)(new T), NULL, BaseTLB::Read);
465 thread->dtb->translateTiming(req, tc, translation, BaseTLB::Read);
466 }
467
468 if (traceData) {
469 traceData->setData(data);
470 traceData->setAddr(addr);
471 }
472
473 // This will need a new way to tell if it has a dcache attached.

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568 _status = DTBWaitResponse;
569 if (split_addr > addr) {
570 RequestPtr req1, req2;
571 assert(!req->isLocked() && !req->isSwap());
572 req->splitOnVaddr(split_addr, req1, req2);
573
574 typedef SplitDataTranslation::WholeTranslationState WholeState;
575 WholeState *state = new WholeState(req1, req2, req,
466 }
467
468 if (traceData) {
469 traceData->setData(data);
470 traceData->setAddr(addr);
471 }
472
473 // This will need a new way to tell if it has a dcache attached.

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568 _status = DTBWaitResponse;
569 if (split_addr > addr) {
570 RequestPtr req1, req2;
571 assert(!req->isLocked() && !req->isSwap());
572 req->splitOnVaddr(split_addr, req1, req2);
573
574 typedef SplitDataTranslation::WholeTranslationState WholeState;
575 WholeState *state = new WholeState(req1, req2, req,
576 (uint8_t *)dataP, false);
576 (uint8_t *)dataP, BaseTLB::Write);
577 thread->dtb->translateTiming(req1, tc,
577 thread->dtb->translateTiming(req1, tc,
578 new SplitDataTranslation(this, 0, state), true);
578 new SplitDataTranslation(this, 0, state), BaseTLB::Write);
579 thread->dtb->translateTiming(req2, tc,
579 thread->dtb->translateTiming(req2, tc,
580 new SplitDataTranslation(this, 1, state), true);
580 new SplitDataTranslation(this, 1, state), BaseTLB::Write);
581 } else {
581 } else {
582 thread->dtb->translateTiming(req, tc,
583 new DataTranslation(this, (uint8_t *)dataP, res, false),
584 true);
582 DataTranslation *translation =
583 new DataTranslation(this, (uint8_t *)dataP, res, BaseTLB::Write);
584 thread->dtb->translateTiming(req, tc, translation, BaseTLB::Write);
585 }
586
587 if (traceData) {
588 traceData->setAddr(req->getVaddr());
589 traceData->setData(data);
590 }
591
592 // This will need a new way to tell if it's hooked up to a cache or not.

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666 checkPcEventQueue();
667
668 bool fromRom = isRomMicroPC(thread->readMicroPC());
669
670 if (!fromRom && !curMacroStaticInst) {
671 Request *ifetch_req = new Request();
672 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
673 setupFetchRequest(ifetch_req);
585 }
586
587 if (traceData) {
588 traceData->setAddr(req->getVaddr());
589 traceData->setData(data);
590 }
591
592 // This will need a new way to tell if it's hooked up to a cache or not.

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666 checkPcEventQueue();
667
668 bool fromRom = isRomMicroPC(thread->readMicroPC());
669
670 if (!fromRom && !curMacroStaticInst) {
671 Request *ifetch_req = new Request();
672 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
673 setupFetchRequest(ifetch_req);
674 thread->itb->translateTiming(ifetch_req, tc,
675 &fetchTranslation, false, true);
674 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
675 BaseTLB::Execute);
676 } else {
677 _status = IcacheWaitResponse;
678 completeIfetch(NULL);
679
680 numCycles += tickToCycles(curTick - previousTick);
681 previousTick = curTick;
682 }
683}

--- 378 unchanged lines hidden --- 		676 } else {
677 _status = IcacheWaitResponse;
678 completeIfetch(NULL);
679
680 numCycles += tickToCycles(curTick - previousTick);
681 previousTick = curTick;
682 }
683}

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