timing.cc (5669:cbac62a59686) timing.cc (5710:b44dd45bd604)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 91 unchanged lines hidden (view full) ---

100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
104 cpu->schedule(this, t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 91 unchanged lines hidden (view full) ---

100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
104 cpu->schedule(this, t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this)
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;
113 dcachePort.snoopRangeSent = false;
114
115 ifetch_pkt = dcache_pkt = NULL;
116 drainEvent = NULL;
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;
113 dcachePort.snoopRangeSent = false;
114
115 ifetch_pkt = dcache_pkt = NULL;
116 drainEvent = NULL;
117 fetchEvent = NULL;
118 previousTick = 0;
119 changeState(SimObject::Running);
120}
121
122
123TimingSimpleCPU::~TimingSimpleCPU()
124{
125}

--- 31 unchanged lines hidden (view full) ---

157
158void
159TimingSimpleCPU::resume()
160{
161 DPRINTF(SimpleCPU, "Resume\n");
162 if (_status != SwitchedOut && _status != Idle) {
163 assert(system->getMemoryMode() == Enums::timing);
164
117 previousTick = 0;
118 changeState(SimObject::Running);
119}
120
121
122TimingSimpleCPU::~TimingSimpleCPU()
123{
124}

--- 31 unchanged lines hidden (view full) ---

156
157void
158TimingSimpleCPU::resume()
159{
160 DPRINTF(SimpleCPU, "Resume\n");
161 if (_status != SwitchedOut && _status != Idle) {
162 assert(system->getMemoryMode() == Enums::timing);
163
165 // Delete the old event if it existed.
166 if (fetchEvent) {
167 if (fetchEvent->scheduled())
168 deschedule(fetchEvent);
164 if (fetchEvent.scheduled())
165 deschedule(fetchEvent);
169
166
170 delete fetchEvent;
171 }
172
173 fetchEvent = new FetchEvent(this, nextCycle());
167 schedule(fetchEvent, nextCycle());
174 }
175
176 changeState(SimObject::Running);
177}
178
179void
180TimingSimpleCPU::switchOut()
181{
182 assert(_status == Running || _status == Idle);
183 _status = SwitchedOut;
184 numCycles += tickToCycles(curTick - previousTick);
185
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
168 }
169
170 changeState(SimObject::Running);
171}
172
173void
174TimingSimpleCPU::switchOut()
175{
176 assert(_status == Running || _status == Idle);
177 _status = SwitchedOut;
178 numCycles += tickToCycles(curTick - previousTick);
179
180 // If we've been scheduled to resume but are then told to switch out,
181 // we'll need to cancel it.
188 if (fetchEvent && fetchEvent->scheduled())
182 if (fetchEvent.scheduled())
189 deschedule(fetchEvent);
190}
191
192
193void
194TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
195{
196 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);

--- 26 unchanged lines hidden (view full) ---

223 assert(thread);
224
225 assert(_status == Idle);
226
227 notIdleFraction++;
228 _status = Running;
229
230 // kick things off by initiating the fetch of the next instruction
183 deschedule(fetchEvent);
184}
185
186
187void
188TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
189{
190 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);

--- 26 unchanged lines hidden (view full) ---

217 assert(thread);
218
219 assert(_status == Idle);
220
221 notIdleFraction++;
222 _status = Running;
223
224 // kick things off by initiating the fetch of the next instruction
231 fetchEvent = new FetchEvent(this);
232 schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
233}
234
235
236void
237TimingSimpleCPU::suspendContext(int thread_num)
238{
239 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);

--- 636 unchanged lines hidden --- 		225 schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
226}
227
228
229void
230TimingSimpleCPU::suspendContext(int thread_num)
231{
232 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);

--- 636 unchanged lines hidden ---