timing.cc (5529:9ae69b9cd7fd) timing.cc (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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96 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
97}
98
99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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96 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
97}
98
99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
104 Event::schedule(t);
104 cpu->schedule(this, t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;

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160{
161 DPRINTF(SimpleCPU, "Resume\n");
162 if (_status != SwitchedOut && _status != Idle) {
163 assert(system->getMemoryMode() == Enums::timing);
164
165 // Delete the old event if it existed.
166 if (fetchEvent) {
167 if (fetchEvent->scheduled())
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;

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160{
161 DPRINTF(SimpleCPU, "Resume\n");
162 if (_status != SwitchedOut && _status != Idle) {
163 assert(system->getMemoryMode() == Enums::timing);
164
165 // Delete the old event if it existed.
166 if (fetchEvent) {
167 if (fetchEvent->scheduled())
168 fetchEvent->deschedule();
168 deschedule(fetchEvent);
169
170 delete fetchEvent;
171 }
172
173 fetchEvent = new FetchEvent(this, nextCycle());
174 }
175
176 changeState(SimObject::Running);

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181{
182 assert(_status == Running || _status == Idle);
183 _status = SwitchedOut;
184 numCycles += tickToCycles(curTick - previousTick);
185
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
188 if (fetchEvent && fetchEvent->scheduled())
169
170 delete fetchEvent;
171 }
172
173 fetchEvent = new FetchEvent(this, nextCycle());
174 }
175
176 changeState(SimObject::Running);

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181{
182 assert(_status == Running || _status == Idle);
183 _status = SwitchedOut;
184 numCycles += tickToCycles(curTick - previousTick);
185
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
188 if (fetchEvent && fetchEvent->scheduled())
189 fetchEvent->deschedule();
189 deschedule(fetchEvent);
190}
191
192
193void
194TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
195{
196 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
197

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223 assert(thread);
224
225 assert(_status == Idle);
226
227 notIdleFraction++;
228 _status = Running;
229
230 // kick things off by initiating the fetch of the next instruction
190}
191
192
193void
194TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
195{
196 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
197

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223 assert(thread);
224
225 assert(_status == Idle);
226
227 notIdleFraction++;
228 _status = Running;
229
230 // kick things off by initiating the fetch of the next instruction
231 fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
231 fetchEvent = new FetchEvent(this);
232 schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
232}
233
234
235void
236TimingSimpleCPU::suspendContext(int thread_num)
237{
238 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
239

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814 PacketPtr tmp = cpu->dcache_pkt;
815 if (sendTiming(tmp)) {
816 cpu->_status = DcacheWaitResponse;
817 // memory system takes ownership of packet
818 cpu->dcache_pkt = NULL;
819 }
820}
821
233}
234
235
236void
237TimingSimpleCPU::suspendContext(int thread_num)
238{
239 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
240

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815 PacketPtr tmp = cpu->dcache_pkt;
816 if (sendTiming(tmp)) {
817 cpu->_status = DcacheWaitResponse;
818 // memory system takes ownership of packet
819 cpu->dcache_pkt = NULL;
820 }
821}
822
822TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
823 : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
823TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
824 Tick t)
825 : pkt(_pkt), cpu(_cpu)
824{
826{
825 schedule(t);
827 cpu->schedule(this, t);
826}
827
828void
829TimingSimpleCPU::IprEvent::process()
830{
831 cpu->completeDataAccess(pkt);
832}
833

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829
830void
831TimingSimpleCPU::IprEvent::process()
832{
833 cpu->completeDataAccess(pkt);
834}
835

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