timing.cc (5507:52bcc301b467) timing.cc (5529:9ae69b9cd7fd)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
104 Event::schedule(t);
105}
106
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103 pkt = _pkt;
104 Event::schedule(t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(Params *p)
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;
113 dcachePort.snoopRangeSent = false;
114
115 ifetch_pkt = dcache_pkt = NULL;

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847
848////////////////////////////////////////////////////////////////////////
849//
850// TimingSimpleCPU Simulation Object
851//
852TimingSimpleCPU *
853TimingSimpleCPUParams::create()
854{
108 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
109{
110 _status = Idle;
111
112 icachePort.snoopRangeSent = false;
113 dcachePort.snoopRangeSent = false;
114
115 ifetch_pkt = dcache_pkt = NULL;

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847
848////////////////////////////////////////////////////////////////////////
849//
850// TimingSimpleCPU Simulation Object
851//
852TimingSimpleCPU *
853TimingSimpleCPUParams::create()
854{
855 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
856 params->name = name;
857 params->numberOfThreads = 1;
858 params->max_insts_any_thread = max_insts_any_thread;
859 params->max_insts_all_threads = max_insts_all_threads;
860 params->max_loads_any_thread = max_loads_any_thread;
861 params->max_loads_all_threads = max_loads_all_threads;
862 params->progress_interval = progress_interval;
863 params->deferRegistration = defer_registration;
864 params->clock = clock;
865 params->phase = phase;
866 params->functionTrace = function_trace;
867 params->functionTraceStart = function_trace_start;
868 params->system = system;
869 params->cpu_id = cpu_id;
870 params->tracer = tracer;
871
872 params->itb = itb;
873 params->dtb = dtb;
874#if FULL_SYSTEM
875 params->profile = profile;
876 params->do_quiesce = do_quiesce;
877 params->do_checkpoint_insts = do_checkpoint_insts;
878 params->do_statistics_insts = do_statistics_insts;
879#else
855 numThreads = 1;
856#if !FULL_SYSTEM
880 if (workload.size() != 1)
881 panic("only one workload allowed");
857 if (workload.size() != 1)
858 panic("only one workload allowed");
882 params->process = workload[0];
883#endif
859#endif
884
885 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
886 return cpu;
860 return new TimingSimpleCPU(this);
887}
861}