timing.cc (5310:4164e6bfcc8a) | timing.cc (5315:30997e988446) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 808 unchanged lines hidden (view full) --- 817 818const char * 819TimingSimpleCPU::IprEvent::description() 820{ 821 return "Timing Simple CPU Delay IPR event"; 822} 823 824 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 808 unchanged lines hidden (view full) --- 817 818const char * 819TimingSimpleCPU::IprEvent::description() 820{ 821 return "Timing Simple CPU Delay IPR event"; 822} 823 824 |
825void 826TimingSimpleCPU::printAddr(Addr a) 827{ 828 dcachePort.printAddr(a); 829} 830 831 |
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825//////////////////////////////////////////////////////////////////////// 826// 827// TimingSimpleCPU Simulation Object 828// 829TimingSimpleCPU * 830TimingSimpleCPUParams::create() 831{ 832 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); --- 32 unchanged lines hidden --- | 832//////////////////////////////////////////////////////////////////////// 833// 834// TimingSimpleCPU Simulation Object 835// 836TimingSimpleCPU * 837TimingSimpleCPUParams::create() 838{ 839 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); --- 32 unchanged lines hidden --- |