timing.cc (5177:4307a768e10e) timing.cc (5221:dba788e614fe)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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152 drainEvent = drain_event;
153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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152 drainEvent = drain_event;
153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
160 DPRINTF(SimpleCPU, "Resume\n");
160 if (_status != SwitchedOut && _status != Idle) {
161 assert(system->getMemoryMode() == Enums::timing);
162
163 // Delete the old event if it existed.
164 if (fetchEvent) {
165 if (fetchEvent->scheduled())
166 fetchEvent->deschedule();
167

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210 cpuId = tc->readCpuId();
211 previousTick = curTick;
212}
213
214
215void
216TimingSimpleCPU::activateContext(int thread_num, int delay)
217{
161 if (_status != SwitchedOut && _status != Idle) {
162 assert(system->getMemoryMode() == Enums::timing);
163
164 // Delete the old event if it existed.
165 if (fetchEvent) {
166 if (fetchEvent->scheduled())
167 fetchEvent->deschedule();
168

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211 cpuId = tc->readCpuId();
212 previousTick = curTick;
213}
214
215
216void
217TimingSimpleCPU::activateContext(int thread_num, int delay)
218{
219 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
220
218 assert(thread_num == 0);
219 assert(thread);
220
221 assert(_status == Idle);
222
223 notIdleFraction++;
224 _status = Running;
225
226 // kick things off by initiating the fetch of the next instruction
227 fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
228}
229
230
231void
232TimingSimpleCPU::suspendContext(int thread_num)
233{
221 assert(thread_num == 0);
222 assert(thread);
223
224 assert(_status == Idle);
225
226 notIdleFraction++;
227 _status = Running;
228
229 // kick things off by initiating the fetch of the next instruction
230 fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
231}
232
233
234void
235TimingSimpleCPU::suspendContext(int thread_num)
236{
237 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
238
234 assert(thread_num == 0);
235 assert(thread);
236
237 assert(_status == Running);
238
239 // just change status to Idle... if status != Running,
240 // completeInst() will not initiate fetch of next instruction.
241

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506{
507 return write((uint32_t)data, addr, flags, res);
508}
509
510
511void
512TimingSimpleCPU::fetch()
513{
239 assert(thread_num == 0);
240 assert(thread);
241
242 assert(_status == Running);
243
244 // just change status to Idle... if status != Running,
245 // completeInst() will not initiate fetch of next instruction.
246

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511{
512 return write((uint32_t)data, addr, flags, res);
513}
514
515
516void
517TimingSimpleCPU::fetch()
518{
519 DPRINTF(SimpleCPU, "Fetch\n");
520
514 if (!curStaticInst || !curStaticInst->isDelayedCommit())
515 checkForInterrupts();
516
517 Request *ifetch_req = new Request();
518 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
519 Fault fault = setupFetchRequest(ifetch_req);
520
521 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);

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555 fetch();
556 }
557}
558
559
560void
561TimingSimpleCPU::completeIfetch(PacketPtr pkt)
562{
521 if (!curStaticInst || !curStaticInst->isDelayedCommit())
522 checkForInterrupts();
523
524 Request *ifetch_req = new Request();
525 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
526 Fault fault = setupFetchRequest(ifetch_req);
527
528 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);

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562 fetch();
563 }
564}
565
566
567void
568TimingSimpleCPU::completeIfetch(PacketPtr pkt)
569{
570 DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
571
563 // received a response from the icache: execute the received
564 // instruction
565 assert(!pkt->isError());
566 assert(_status == IcacheWaitResponse);
567
568 _status = Running;
569
570 numCycles += tickToCycles(curTick - previousTick);

--- 284 unchanged lines hidden --- 		572 // received a response from the icache: execute the received
573 // instruction
574 assert(!pkt->isError());
575 assert(_status == IcacheWaitResponse);
576
577 _status = Running;
578
579 numCycles += tickToCycles(curTick - previousTick);

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