timing.cc (5169:bfd18d401251) timing.cc (5177:4307a768e10e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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288 recordEvent("Uncached Read");
289 } else {
290 delete req;
291 }
292
293 return fault;
294}
295
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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288 recordEvent("Uncached Read");
289 } else {
290 delete req;
291 }
292
293 return fault;
294}
295
296Fault
297TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
298 int size, unsigned flags)
299{
300 Request *req =
301 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
302
303 if (traceData) {
304 traceData->setAddr(vaddr);
305 }
306
307 Fault fault = thread->translateDataWriteReq(req);
308
309 if (fault == NoFault)
310 paddr = req->getPaddr();
311
312 delete req;
313 return fault;
314}
315
296#ifndef DOXYGEN_SHOULD_SKIP_THIS
297
298template
299Fault
300TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
301
302template
303Fault

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406 }
407
408
409 // If the write needs to have a fault on the access, consider calling
410 // changeStatus() and changing it to "bad addr write" or something.
411 return fault;
412}
413
316#ifndef DOXYGEN_SHOULD_SKIP_THIS
317
318template
319Fault
320TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
321
322template
323Fault

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426 }
427
428
429 // If the write needs to have a fault on the access, consider calling
430 // changeStatus() and changing it to "bad addr write" or something.
431 return fault;
432}
433
434Fault
435TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
436 int size, unsigned flags)
437{
438 Request *req =
439 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
414
440
441 if (traceData) {
442 traceData->setAddr(vaddr);
443 }
444
445 Fault fault = thread->translateDataWriteReq(req);
446
447 if (fault == NoFault)
448 paddr = req->getPaddr();
449
450 delete req;
451 return fault;
452}
453
454
415#ifndef DOXYGEN_SHOULD_SKIP_THIS
416template
417Fault
418TimingSimpleCPU::write(Twin32_t data, Addr addr,
419 unsigned flags, uint64_t *res);
420
421template
422Fault

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456template
457Fault
458TimingSimpleCPU::write(Twin32_t data, Addr addr,
459 unsigned flags, uint64_t *res);
460
461template
462Fault

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