timing.cc (5101:8af5a6a6223d) timing.cc (5103:391933804192)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
32#include "arch/utility.hh"
33#include "base/bigint.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/timing.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "params/TimingSimpleCPU.hh"
39#include "sim/system.hh"

--- 221 unchanged lines hidden (view full) ---

261 if (fault == NoFault) {
262 PacketPtr pkt =
263 new Packet(req,
264 (req->isLocked() ?
265 MemCmd::LoadLockedReq : MemCmd::ReadReq),
266 Packet::Broadcast);
267 pkt->dataDynamic<T>(new T);
268
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/timing.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/TimingSimpleCPU.hh"
40#include "sim/system.hh"

--- 221 unchanged lines hidden (view full) ---

262 if (fault == NoFault) {
263 PacketPtr pkt =
264 new Packet(req,
265 (req->isLocked() ?
266 MemCmd::LoadLockedReq : MemCmd::ReadReq),
267 Packet::Broadcast);
268 pkt->dataDynamic<T>(new T);
269
269 if (!dcachePort.sendTiming(pkt)) {
270 if (req->isMmapedIpr()) {
271 Tick delay;
272 delay = TheISA::handleIprRead(thread->getTC(), pkt);
273 new IprEvent(pkt, this, nextCycle(curTick + delay));
274 _status = DcacheWaitResponse;
275 dcache_pkt = NULL;
276 } else if (!dcachePort.sendTiming(pkt)) {
270 _status = DcacheRetry;
271 dcache_pkt = pkt;
272 } else {
273 _status = DcacheWaitResponse;
274 // memory system takes ownership of packet
275 dcache_pkt = NULL;
276 }
277

--- 92 unchanged lines hidden (view full) ---

370 // Note: need to allocate dcache_pkt even if do_access is
371 // false, as it's used unconditionally to call completeAcc().
372 assert(dcache_pkt == NULL);
373 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
374 dcache_pkt->allocate();
375 dcache_pkt->set(data);
376
377 if (do_access) {
277 _status = DcacheRetry;
278 dcache_pkt = pkt;
279 } else {
280 _status = DcacheWaitResponse;
281 // memory system takes ownership of packet
282 dcache_pkt = NULL;
283 }
284

--- 92 unchanged lines hidden (view full) ---

377 // Note: need to allocate dcache_pkt even if do_access is
378 // false, as it's used unconditionally to call completeAcc().
379 assert(dcache_pkt == NULL);
380 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
381 dcache_pkt->allocate();
382 dcache_pkt->set(data);
383
384 if (do_access) {
378 if (!dcachePort.sendTiming(dcache_pkt)) {
385 if (req->isMmapedIpr()) {
386 Tick delay;
387 dcache_pkt->set(htog(data));
388 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
389 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
390 _status = DcacheWaitResponse;
391 dcache_pkt = NULL;
392 } else if (!dcachePort.sendTiming(dcache_pkt)) {
379 _status = DcacheRetry;
380 } else {
381 _status = DcacheWaitResponse;
382 // memory system takes ownership of packet
383 dcache_pkt = NULL;
384 }
385 }
386 // This will need a new way to tell if it's hooked up to a cache or not.

--- 159 unchanged lines hidden (view full) ---

546 countInst();
547 } else if (traceData) {
548 // If there was a fault, we shouldn't trace this instruction.
549 delete traceData;
550 traceData = NULL;
551 }
552
553 postExecute();
393 _status = DcacheRetry;
394 } else {
395 _status = DcacheWaitResponse;
396 // memory system takes ownership of packet
397 dcache_pkt = NULL;
398 }
399 }
400 // This will need a new way to tell if it's hooked up to a cache or not.

--- 159 unchanged lines hidden (view full) ---

560 countInst();
561 } else if (traceData) {
562 // If there was a fault, we shouldn't trace this instruction.
563 delete traceData;
564 traceData = NULL;
565 }
566
567 postExecute();
568 // @todo remove me after debugging with legion done
569 if (curStaticInst && (!curStaticInst->isMicroop() ||
570 curStaticInst->isFirstMicroop()))
571 instCnt++;
554 advanceInst(fault);
555 }
556 } else {
557 // non-memory instruction: execute completely now
558 Fault fault = curStaticInst->execute(this, traceData);
559
560 // keep an instruction count
561 if (fault == NoFault)
562 countInst();
563 else if (traceData) {
564 // If there was a fault, we shouldn't trace this instruction.
565 delete traceData;
566 traceData = NULL;
567 }
568
569 postExecute();
572 advanceInst(fault);
573 }
574 } else {
575 // non-memory instruction: execute completely now
576 Fault fault = curStaticInst->execute(this, traceData);
577
578 // keep an instruction count
579 if (fault == NoFault)
580 countInst();
581 else if (traceData) {
582 // If there was a fault, we shouldn't trace this instruction.
583 delete traceData;
584 traceData = NULL;
585 }
586
587 postExecute();
588 // @todo remove me after debugging with legion done
589 if (curStaticInst && (!curStaticInst->isMicroop() ||
590 curStaticInst->isFirstMicroop()))
591 instCnt++;
570 advanceInst(fault);
571 }
572
573 delete pkt->req;
574 delete pkt;
575}
576
577void

--- 147 unchanged lines hidden (view full) ---

725 PacketPtr tmp = cpu->dcache_pkt;
726 if (sendTiming(tmp)) {
727 cpu->_status = DcacheWaitResponse;
728 // memory system takes ownership of packet
729 cpu->dcache_pkt = NULL;
730 }
731}
732
592 advanceInst(fault);
593 }
594
595 delete pkt->req;
596 delete pkt;
597}
598
599void

--- 147 unchanged lines hidden (view full) ---

747 PacketPtr tmp = cpu->dcache_pkt;
748 if (sendTiming(tmp)) {
749 cpu->_status = DcacheWaitResponse;
750 // memory system takes ownership of packet
751 cpu->dcache_pkt = NULL;
752 }
753}
754
755TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
756 : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
757{
758 schedule(t);
759}
733
760
761void
762TimingSimpleCPU::IprEvent::process()
763{
764 cpu->completeDataAccess(pkt);
765}
766
767const char *
768TimingSimpleCPU::IprEvent::description()
769{
770 return "Timing Simple CPU Delay IPR event";
771}
772
773
734////////////////////////////////////////////////////////////////////////
735//
736// TimingSimpleCPU Simulation Object
737//
738TimingSimpleCPU *
739TimingSimpleCPUParams::create()
740{
741 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();

--- 32 unchanged lines hidden --- 		774////////////////////////////////////////////////////////////////////////
775//
776// TimingSimpleCPU Simulation Object
777//
778TimingSimpleCPU *
779TimingSimpleCPUParams::create()
780{
781 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();

--- 32 unchanged lines hidden ---