timing.cc (4928:951bd17db218) timing.cc (4986:b7c82ad6b3ef)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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559TimingSimpleCPU::IcachePort::ITickEvent::process()
560{
561 cpu->completeIfetch(pkt);
562}
563
564bool
565TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
566{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 550 unchanged lines hidden (view full) ---

559TimingSimpleCPU::IcachePort::ITickEvent::process()
560{
561 cpu->completeIfetch(pkt);
562}
563
564bool
565TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
566{
567 if (pkt->isResponse()) {
567 if (pkt->isResponse() && !pkt->wasNacked()) {
568 // delay processing of returned data until next CPU clock edge
569 Tick next_tick = cpu->nextCycle(curTick);
570
571 if (next_tick == curTick)
572 cpu->completeIfetch(pkt);
573 else
574 tickEvent.schedule(pkt, next_tick);
575

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653 // Ports)
654 cpu->tcBase()->connectMemPorts();
655#endif
656}
657
658bool
659TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
660{
568 // delay processing of returned data until next CPU clock edge
569 Tick next_tick = cpu->nextCycle(curTick);
570
571 if (next_tick == curTick)
572 cpu->completeIfetch(pkt);
573 else
574 tickEvent.schedule(pkt, next_tick);
575

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653 // Ports)
654 cpu->tcBase()->connectMemPorts();
655#endif
656}
657
658bool
659TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
660{
661 if (pkt->isResponse()) {
661 if (pkt->isResponse() && !pkt->wasNacked()) {
662 // delay processing of returned data until next CPU clock edge
663 Tick next_tick = cpu->nextCycle(curTick);
664
665 if (next_tick == curTick)
666 cpu->completeDataAccess(pkt);
667 else
668 tickEvent.schedule(pkt, next_tick);
669

--- 76 unchanged lines hidden --- 		662 // delay processing of returned data until next CPU clock edge
663 Tick next_tick = cpu->nextCycle(curTick);
664
665 if (next_tick == curTick)
666 cpu->completeDataAccess(pkt);
667 else
668 tickEvent.schedule(pkt, next_tick);
669

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