timing.cc (4881:3e4b4f6ff9dd) timing.cc (4918:3214e3694fb2)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "base/bigint.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/timing.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "base/bigint.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/timing.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "sim/builder.hh"
38#include "params/TimingSimpleCPU.hh"
39#include "sim/system.hh"
40
41using namespace std;
42using namespace TheISA;
43
44Port *
45TimingSimpleCPU::getPort(const std::string &if_name, int idx)
46{

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153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
160 if (_status != SwitchedOut && _status != Idle) {
39#include "sim/system.hh"
40
41using namespace std;
42using namespace TheISA;
43
44Port *
45TimingSimpleCPU::getPort(const std::string &if_name, int idx)
46{

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153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
160 if (_status != SwitchedOut && _status != Idle) {
161 assert(system->getMemoryMode() == System::Timing);
161 assert(system->getMemoryMode() == Enums::timing);
162
163 // Delete the old event if it existed.
164 if (fetchEvent) {
165 if (fetchEvent->scheduled())
166 fetchEvent->deschedule();
167
168 delete fetchEvent;
169 }

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702 }
703}
704
705
706////////////////////////////////////////////////////////////////////////
707//
708// TimingSimpleCPU Simulation Object
709//
162
163 // Delete the old event if it existed.
164 if (fetchEvent) {
165 if (fetchEvent->scheduled())
166 fetchEvent->deschedule();
167
168 delete fetchEvent;
169 }

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702 }
703}
704
705
706////////////////////////////////////////////////////////////////////////
707//
708// TimingSimpleCPU Simulation Object
709//
710BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
711
712 Param<Counter> max_insts_any_thread;
713 Param<Counter> max_insts_all_threads;
714 Param<Counter> max_loads_any_thread;
715 Param<Counter> max_loads_all_threads;
716 Param<Tick> progress_interval;
717 SimObjectParam<System *> system;
718 Param<int> cpu_id;
719
720#if FULL_SYSTEM
721 SimObjectParam<TheISA::ITB *> itb;
722 SimObjectParam<TheISA::DTB *> dtb;
723 Param<Tick> profile;
724
725 Param<bool> do_quiesce;
726 Param<bool> do_checkpoint_insts;
727 Param<bool> do_statistics_insts;
728#else
729 SimObjectParam<Process *> workload;
730#endif // FULL_SYSTEM
731
732 Param<int> clock;
733 Param<int> phase;
734
735 Param<bool> defer_registration;
736 Param<int> width;
737 Param<bool> function_trace;
738 Param<Tick> function_trace_start;
739 Param<bool> simulate_stalls;
740
741END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
742
743BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
744
745 INIT_PARAM(max_insts_any_thread,
746 "terminate when any thread reaches this inst count"),
747 INIT_PARAM(max_insts_all_threads,
748 "terminate when all threads have reached this inst count"),
749 INIT_PARAM(max_loads_any_thread,
750 "terminate when any thread reaches this load count"),
751 INIT_PARAM(max_loads_all_threads,
752 "terminate when all threads have reached this load count"),
753 INIT_PARAM(progress_interval, "Progress interval"),
754 INIT_PARAM(system, "system object"),
755 INIT_PARAM(cpu_id, "processor ID"),
756
757#if FULL_SYSTEM
758 INIT_PARAM(itb, "Instruction TLB"),
759 INIT_PARAM(dtb, "Data TLB"),
760 INIT_PARAM(profile, ""),
761 INIT_PARAM(do_quiesce, ""),
762 INIT_PARAM(do_checkpoint_insts, ""),
763 INIT_PARAM(do_statistics_insts, ""),
764#else
765 INIT_PARAM(workload, "processes to run"),
766#endif // FULL_SYSTEM
767
768 INIT_PARAM(clock, "clock speed"),
769 INIT_PARAM_DFLT(phase, "clock phase", 0),
770 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
771 INIT_PARAM(width, "cpu width"),
772 INIT_PARAM(function_trace, "Enable function trace"),
773 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
774 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
775
776END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
777
778
779CREATE_SIM_OBJECT(TimingSimpleCPU)
710TimingSimpleCPU *
711TimingSimpleCPUParams::create()
780{
781 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
712{
713 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
782 params->name = getInstanceName();
714 params->name = name;
783 params->numberOfThreads = 1;
784 params->max_insts_any_thread = max_insts_any_thread;
785 params->max_insts_all_threads = max_insts_all_threads;
786 params->max_loads_any_thread = max_loads_any_thread;
787 params->max_loads_all_threads = max_loads_all_threads;
788 params->progress_interval = progress_interval;
789 params->deferRegistration = defer_registration;
790 params->clock = clock;

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797#if FULL_SYSTEM
798 params->itb = itb;
799 params->dtb = dtb;
800 params->profile = profile;
801 params->do_quiesce = do_quiesce;
802 params->do_checkpoint_insts = do_checkpoint_insts;
803 params->do_statistics_insts = do_statistics_insts;
804#else
715 params->numberOfThreads = 1;
716 params->max_insts_any_thread = max_insts_any_thread;
717 params->max_insts_all_threads = max_insts_all_threads;
718 params->max_loads_any_thread = max_loads_any_thread;
719 params->max_loads_all_threads = max_loads_all_threads;
720 params->progress_interval = progress_interval;
721 params->deferRegistration = defer_registration;
722 params->clock = clock;

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729#if FULL_SYSTEM
730 params->itb = itb;
731 params->dtb = dtb;
732 params->profile = profile;
733 params->do_quiesce = do_quiesce;
734 params->do_checkpoint_insts = do_checkpoint_insts;
735 params->do_statistics_insts = do_statistics_insts;
736#else
805 params->process = workload;
737 if (workload.size() != 1)
738 panic("only one workload allowed");
739 params->process = workload[0];
806#endif
807
808 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
809 return cpu;
810}
740#endif
741
742 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
743 return cpu;
744}
811
812REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
813