timing.cc (4870:fcc39d001154) timing.cc (4878:5b747482d2d8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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255 }
256
257 // translate to physical address
258 Fault fault = thread->translateDataReadReq(req);
259
260 // Now do the access.
261 if (fault == NoFault) {
262 PacketPtr pkt =
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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255 }
256
257 // translate to physical address
258 Fault fault = thread->translateDataReadReq(req);
259
260 // Now do the access.
261 if (fault == NoFault) {
262 PacketPtr pkt =
263 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
263 new Packet(req,
264 (req->isLocked() ?
265 MemCmd::LoadLockedReq : MemCmd::ReadReq),
266 Packet::Broadcast);
264 pkt->dataDynamic<T>(new T);
265
266 if (!dcachePort.sendTiming(pkt)) {
267 _status = DcacheRetry;
268 dcache_pkt = pkt;
269 } else {
270 _status = DcacheWaitResponse;
271 // memory system takes ownership of packet

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345 traceData->setAddr(req->getVaddr());
346 }
347
348 // translate to physical address
349 Fault fault = thread->translateDataWriteReq(req);
350
351 // Now do the access.
352 if (fault == NoFault) {
267 pkt->dataDynamic<T>(new T);
268
269 if (!dcachePort.sendTiming(pkt)) {
270 _status = DcacheRetry;
271 dcache_pkt = pkt;
272 } else {
273 _status = DcacheWaitResponse;
274 // memory system takes ownership of packet

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348 traceData->setAddr(req->getVaddr());
349 }
350
351 // translate to physical address
352 Fault fault = thread->translateDataWriteReq(req);
353
354 // Now do the access.
355 if (fault == NoFault) {
353 assert(dcache_pkt == NULL);
354 if (req->isSwap())
355 dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
356 else
357 dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
358 dcache_pkt->allocate();
359 dcache_pkt->set(data);
360
356 MemCmd cmd = MemCmd::WriteReq; // default
361 bool do_access = true; // flag to suppress cache access
362
357 bool do_access = true; // flag to suppress cache access
358
359 assert(dcache_pkt == NULL);
360
363 if (req->isLocked()) {
361 if (req->isLocked()) {
362 cmd = MemCmd::StoreCondReq;
364 do_access = TheISA::handleLockedWrite(thread, req);
363 do_access = TheISA::handleLockedWrite(thread, req);
364 } else if (req->isSwap()) {
365 cmd = MemCmd::SwapReq;
366 if (req->isCondSwap()) {
367 assert(res);
368 req->setExtraData(*res);
369 }
365 }
370 }
366 if (req->isCondSwap()) {
367 assert(res);
368 req->setExtraData(*res);
369 }
370
371 if (do_access) {
371
372 if (do_access) {
373 dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
374 dcache_pkt->allocate();
375 dcache_pkt->set(data);
376
372 if (!dcachePort.sendTiming(dcache_pkt)) {
373 _status = DcacheRetry;
374 } else {
375 _status = DcacheWaitResponse;
376 // memory system takes ownership of packet
377 dcache_pkt = NULL;
378 }
379 }

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604 assert(_status == DcacheWaitResponse);
605 _status = Running;
606
607 numCycles += curTick - previousTick;
608 previousTick = curTick;
609
610 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
611
377 if (!dcachePort.sendTiming(dcache_pkt)) {
378 _status = DcacheRetry;
379 } else {
380 _status = DcacheWaitResponse;
381 // memory system takes ownership of packet
382 dcache_pkt = NULL;
383 }
384 }

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609 assert(_status == DcacheWaitResponse);
610 _status = Running;
611
612 numCycles += curTick - previousTick;
613 previousTick = curTick;
614
615 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
616
612 if (pkt->isRead() && pkt->req->isLocked()) {
617 if (pkt->isRead() && pkt->isLocked()) {
613 TheISA::handleLockedRead(thread, pkt->req);
614 }
615
616 delete pkt->req;
617 delete pkt;
618
619 postExecute();
620

--- 187 unchanged lines hidden --- 		618 TheISA::handleLockedRead(thread, pkt->req);
619 }
620
621 delete pkt->req;
622 delete pkt;
623
624 postExecute();
625

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