timing.cc (4471:4d86c4d096ad) timing.cc (4584:81a11c930f2d)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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555 cpu->completeIfetch(pkt);
556}
557
558bool
559TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
560{
561 if (pkt->isResponse()) {
562 // delay processing of returned data until next CPU clock edge
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 546 unchanged lines hidden (view full) ---

555 cpu->completeIfetch(pkt);
556}
557
558bool
559TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
560{
561 if (pkt->isResponse()) {
562 // delay processing of returned data until next CPU clock edge
563 Tick mem_time = pkt->req->getTime();
564 Tick next_tick = cpu->nextCycle(mem_time);
563 Tick next_tick = cpu->nextCycle(curTick);
565
566 if (next_tick == curTick)
567 cpu->completeIfetch(pkt);
568 else
569 tickEvent.schedule(pkt, next_tick);
570
571 return true;
572 }

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650#endif
651}
652
653bool
654TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
655{
656 if (pkt->isResponse()) {
657 // delay processing of returned data until next CPU clock edge
564
565 if (next_tick == curTick)
566 cpu->completeIfetch(pkt);
567 else
568 tickEvent.schedule(pkt, next_tick);
569
570 return true;
571 }

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649#endif
650}
651
652bool
653TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
654{
655 if (pkt->isResponse()) {
656 // delay processing of returned data until next CPU clock edge
658 Tick mem_time = pkt->req->getTime();
659 Tick next_tick = cpu->nextCycle(mem_time);
657 Tick next_tick = cpu->nextCycle(curTick);
660
661 if (next_tick == curTick)
662 cpu->completeDataAccess(pkt);
663 else
664 tickEvent.schedule(pkt, next_tick);
665
666 return true;
667 }

--- 142 unchanged lines hidden --- 		658
659 if (next_tick == curTick)
660 cpu->completeDataAccess(pkt);
661 else
662 tickEvent.schedule(pkt, next_tick);
663
664 return true;
665 }

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