timing.cc (4192:7accc6365bb9) timing.cc (4200:f55b59fc848b)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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270 if (!dcachePort.sendTiming(pkt)) {
271 _status = DcacheRetry;
272 dcache_pkt = pkt;
273 } else {
274 _status = DcacheWaitResponse;
275 // memory system takes ownership of packet
276 dcache_pkt = NULL;
277 }
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 261 unchanged lines hidden (view full) ---

270 if (!dcachePort.sendTiming(pkt)) {
271 _status = DcacheRetry;
272 dcache_pkt = pkt;
273 } else {
274 _status = DcacheWaitResponse;
275 // memory system takes ownership of packet
276 dcache_pkt = NULL;
277 }
278
279 // This will need a new way to tell if it has a dcache attached.
280 if (req->isUncacheable())
281 recordEvent("Uncached Read");
278 } else {
279 delete req;
280 }
281
282 } else {
283 delete req;
284 }
285
282 // This will need a new way to tell if it has a dcache attached.
283 if (req->isUncacheable())
284 recordEvent("Uncached Read");
285
286 return fault;
287}
288
289#ifndef DOXYGEN_SHOULD_SKIP_THIS
290
291template
292Fault
293TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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376 if (!dcachePort.sendTiming(dcache_pkt)) {
377 _status = DcacheRetry;
378 } else {
379 _status = DcacheWaitResponse;
380 // memory system takes ownership of packet
381 dcache_pkt = NULL;
382 }
383 }
286 return fault;
287}
288
289#ifndef DOXYGEN_SHOULD_SKIP_THIS
290
291template
292Fault
293TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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376 if (!dcachePort.sendTiming(dcache_pkt)) {
377 _status = DcacheRetry;
378 } else {
379 _status = DcacheWaitResponse;
380 // memory system takes ownership of packet
381 dcache_pkt = NULL;
382 }
383 }
384 // This will need a new way to tell if it's hooked up to a cache or not.
385 if (req->isUncacheable())
386 recordEvent("Uncached Write");
384 } else {
385 delete req;
386 }
387
387 } else {
388 delete req;
389 }
390
388 // This will need a new way to tell if it's hooked up to a cache or not.
389 if (req->isUncacheable())
390 recordEvent("Uncached Write");
391
392 // If the write needs to have a fault on the access, consider calling
393 // changeStatus() and changing it to "bad addr write" or something.
394 return fault;
395}
396
397
398#ifndef DOXYGEN_SHOULD_SKIP_THIS

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392 // If the write needs to have a fault on the access, consider calling
393 // changeStatus() and changing it to "bad addr write" or something.
394 return fault;
395}
396
397
398#ifndef DOXYGEN_SHOULD_SKIP_THIS

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