timing.cc (4115:cc1d6df13c7d) timing.cc (4192:7accc6365bb9)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 180 unchanged lines hidden (view full) ---

189 if (fetchEvent && fetchEvent->scheduled())
190 fetchEvent->deschedule();
191}
192
193
194void
195TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
196{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 180 unchanged lines hidden (view full) ---

189 if (fetchEvent && fetchEvent->scheduled())
190 fetchEvent->deschedule();
191}
192
193
194void
195TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
196{
197 BaseCPU::takeOverFrom(oldCPU);
197 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
198
199 // if any of this CPU's ThreadContexts are active, mark the CPU as
200 // running and schedule its tick event.
201 for (int i = 0; i < threadContexts.size(); ++i) {
202 ThreadContext *tc = threadContexts[i];
203 if (tc->status() == ThreadContext::Active && _status != Running) {
204 _status = Running;
205 break;
206 }
207 }
208
209 if (_status != Running) {
210 _status = Idle;
211 }
198
199 // if any of this CPU's ThreadContexts are active, mark the CPU as
200 // running and schedule its tick event.
201 for (int i = 0; i < threadContexts.size(); ++i) {
202 ThreadContext *tc = threadContexts[i];
203 if (tc->status() == ThreadContext::Active && _status != Running) {
204 _status = Running;
205 break;
206 }
207 }
208
209 if (_status != Running) {
210 _status = Idle;
211 }
212
213 Port *peer;
214 if (icachePort.getPeer() == NULL) {
215 peer = oldCPU->getPort("icache_port")->getPeer();
216 icachePort.setPeer(peer);
217 } else {
218 peer = icachePort.getPeer();
219 }
220 peer->setPeer(&icachePort);
221
222 if (dcachePort.getPeer() == NULL) {
223 peer = oldCPU->getPort("dcache_port")->getPeer();
224 dcachePort.setPeer(peer);
225 } else {
226 peer = dcachePort.getPeer();
227 }
228 peer->setPeer(&dcachePort);
229}
230
231
232void
233TimingSimpleCPU::activateContext(int thread_num, int delay)
234{
235 assert(thread_num == 0);
236 assert(thread);
237
238 assert(_status == Idle);
239
240 notIdleFraction++;
241 _status = Running;
242
212}
213
214
215void
216TimingSimpleCPU::activateContext(int thread_num, int delay)
217{
218 assert(thread_num == 0);
219 assert(thread);
220
221 assert(_status == Idle);
222
223 notIdleFraction++;
224 _status = Running;
225
243#if FULL_SYSTEM
244 // Connect the ThreadContext's memory ports (Functional/Virtual
245 // Ports)
246 tc->connectMemPorts();
247#endif
248
249 // kick things off by initiating the fetch of the next instruction
250 fetchEvent =
251 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
252 fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
253}
254
255
256void

--- 387 unchanged lines hidden (view full) ---

644void
645TimingSimpleCPU::completeDrain()
646{
647 DPRINTF(Config, "Done draining\n");
648 changeState(SimObject::Drained);
649 drainEvent->process();
650}
651
226 // kick things off by initiating the fetch of the next instruction
227 fetchEvent =
228 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
229 fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
230}
231
232
233void

--- 387 unchanged lines hidden (view full) ---

621void
622TimingSimpleCPU::completeDrain()
623{
624 DPRINTF(Config, "Done draining\n");
625 changeState(SimObject::Drained);
626 drainEvent->process();
627}
628
629void
630TimingSimpleCPU::DcachePort::setPeer(Port *port)
631{
632 Port::setPeer(port);
633
634#if FULL_SYSTEM
635 // Update the ThreadContext's memory ports (Functional/Virtual
636 // Ports)
637 cpu->tcBase()->connectMemPorts();
638#endif
639}
640
652bool
653TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
654{
655 if (pkt->isResponse()) {
656 // delay processing of returned data until next CPU clock edge
657 Tick mem_time = pkt->req->getTime();
658 Tick next_tick = cpu->nextCycle(mem_time);
659

--- 143 unchanged lines hidden --- 		641bool
642TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
643{
644 if (pkt->isResponse()) {
645 // delay processing of returned data until next CPU clock edge
646 Tick mem_time = pkt->req->getTime();
647 Tick next_tick = cpu->nextCycle(mem_time);
648

--- 143 unchanged lines hidden ---