timing.cc (4022:c422464ca16e) timing.cc (4040:eb894f3fc168)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "base/bigint.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/timing.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;

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307
308 return fault;
309}
310
311#ifndef DOXYGEN_SHOULD_SKIP_THIS
312
313template
314Fault
34#include "cpu/exetrace.hh"
35#include "cpu/simple/timing.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "sim/builder.hh"
39#include "sim/system.hh"
40
41using namespace std;

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308
309 return fault;
310}
311
312#ifndef DOXYGEN_SHOULD_SKIP_THIS
313
314template
315Fault
316TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
317
318template
319Fault
315TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
316
317template
318Fault
319TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
320
321template
322Fault

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354template <class T>
355Fault
356TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
357{
358 Request *req =
359 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
360 cpu_id, /* thread ID */ 0);
361
320TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
321
322template
323Fault
324TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
325
326template
327Fault

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359template <class T>
360Fault
361TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
362{
363 Request *req =
364 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
365 cpu_id, /* thread ID */ 0);
366
367 if (traceData) {
368 traceData->setAddr(req->getVaddr());
369 }
370
362 // translate to physical address
363 Fault fault = thread->translateDataWriteReq(req);
364
365 // Now do the access.
366 if (fault == NoFault) {
367 assert(dcache_pkt == NULL);
371 // translate to physical address
372 Fault fault = thread->translateDataWriteReq(req);
373
374 // Now do the access.
375 if (fault == NoFault) {
376 assert(dcache_pkt == NULL);
368 dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
377 if (req->isSwap())
378 dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
379 else
380 dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
369 dcache_pkt->allocate();
370 dcache_pkt->set(data);
371
372 bool do_access = true; // flag to suppress cache access
373
374 if (req->isLocked()) {
375 do_access = TheISA::handleLockedWrite(thread, req);
376 }
381 dcache_pkt->allocate();
382 dcache_pkt->set(data);
383
384 bool do_access = true; // flag to suppress cache access
385
386 if (req->isLocked()) {
387 do_access = TheISA::handleLockedWrite(thread, req);
388 }
389 if (req->isCondSwap()) {
390 assert(res);
391 req->setExtraData(*res);
392 }
377
378 if (do_access) {
379 if (!dcachePort.sendTiming(dcache_pkt)) {
380 _status = DcacheRetry;
381 } else {
382 _status = DcacheWaitResponse;
383 // memory system takes ownership of packet
384 dcache_pkt = NULL;

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394 if (do_access) {
395 if (!dcachePort.sendTiming(dcache_pkt)) {
396 _status = DcacheRetry;
397 } else {
398 _status = DcacheWaitResponse;
399 // memory system takes ownership of packet
400 dcache_pkt = NULL;

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