timing.cc (3686:fa8d8b90cd8a) timing.cc (4022:c422464ca16e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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281 }
282
283 // translate to physical address
284 Fault fault = thread->translateDataReadReq(req);
285
286 // Now do the access.
287 if (fault == NoFault) {
288 PacketPtr pkt =
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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281 }
282
283 // translate to physical address
284 Fault fault = thread->translateDataReadReq(req);
285
286 // Now do the access.
287 if (fault == NoFault) {
288 PacketPtr pkt =
289 new Packet(req, Packet::ReadReq, Packet::Broadcast);
289 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
290 pkt->dataDynamic<T>(new T);
291
292 if (!dcachePort.sendTiming(pkt)) {
293 _status = DcacheRetry;
294 dcache_pkt = pkt;
295 } else {
296 _status = DcacheWaitResponse;
297 // memory system takes ownership of packet

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360 cpu_id, /* thread ID */ 0);
361
362 // translate to physical address
363 Fault fault = thread->translateDataWriteReq(req);
364
365 // Now do the access.
366 if (fault == NoFault) {
367 assert(dcache_pkt == NULL);
290 pkt->dataDynamic<T>(new T);
291
292 if (!dcachePort.sendTiming(pkt)) {
293 _status = DcacheRetry;
294 dcache_pkt = pkt;
295 } else {
296 _status = DcacheWaitResponse;
297 // memory system takes ownership of packet

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360 cpu_id, /* thread ID */ 0);
361
362 // translate to physical address
363 Fault fault = thread->translateDataWriteReq(req);
364
365 // Now do the access.
366 if (fault == NoFault) {
367 assert(dcache_pkt == NULL);
368 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
368 dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
369 dcache_pkt->allocate();
370 dcache_pkt->set(data);
371
372 bool do_access = true; // flag to suppress cache access
373
374 if (req->isLocked()) {
375 do_access = TheISA::handleLockedWrite(thread, req);
376 }

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449{
450 if (!curStaticInst || !curStaticInst->isDelayedCommit())
451 checkForInterrupts();
452
453 Request *ifetch_req = new Request();
454 ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
455 Fault fault = setupFetchRequest(ifetch_req);
456
369 dcache_pkt->allocate();
370 dcache_pkt->set(data);
371
372 bool do_access = true; // flag to suppress cache access
373
374 if (req->isLocked()) {
375 do_access = TheISA::handleLockedWrite(thread, req);
376 }

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449{
450 if (!curStaticInst || !curStaticInst->isDelayedCommit())
451 checkForInterrupts();
452
453 Request *ifetch_req = new Request();
454 ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
455 Fault fault = setupFetchRequest(ifetch_req);
456
457 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
457 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
458 ifetch_pkt->dataStatic(&inst);
459
460 if (fault == NoFault) {
461 if (!icachePort.sendTiming(ifetch_pkt)) {
462 // Need to wait for retry
463 _status = IcacheRetry;
464 } else {
465 // Need to wait for cache to respond

--- 317 unchanged lines hidden --- 		458 ifetch_pkt->dataStatic(&inst);
459
460 if (fault == NoFault) {
461 if (!icachePort.sendTiming(ifetch_pkt)) {
462 // Need to wait for retry
463 _status = IcacheRetry;
464 } else {
465 // Need to wait for cache to respond

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