timing.cc (3661:efc80a01aeb6) timing.cc (3667:1d57100f8bf0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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285 if (!dcachePort.sendTiming(pkt)) {
286 _status = DcacheRetry;
287 dcache_pkt = pkt;
288 } else {
289 _status = DcacheWaitResponse;
290 // memory system takes ownership of packet
291 dcache_pkt = NULL;
292 }
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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285 if (!dcachePort.sendTiming(pkt)) {
286 _status = DcacheRetry;
287 dcache_pkt = pkt;
288 } else {
289 _status = DcacheWaitResponse;
290 // memory system takes ownership of packet
291 dcache_pkt = NULL;
292 }
293 } else {
294 delete req;
293 }
294
295 // This will need a new way to tell if it has a dcache attached.
296 if (req->isUncacheable())
297 recordEvent("Uncached Read");
298
299 return fault;
300}

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370 if (!dcachePort.sendTiming(dcache_pkt)) {
371 _status = DcacheRetry;
372 } else {
373 _status = DcacheWaitResponse;
374 // memory system takes ownership of packet
375 dcache_pkt = NULL;
376 }
377 }
295 }
296
297 // This will need a new way to tell if it has a dcache attached.
298 if (req->isUncacheable())
299 recordEvent("Uncached Read");
300
301 return fault;
302}

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372 if (!dcachePort.sendTiming(dcache_pkt)) {
373 _status = DcacheRetry;
374 } else {
375 _status = DcacheWaitResponse;
376 // memory system takes ownership of packet
377 dcache_pkt = NULL;
378 }
379 }
380 } else {
381 delete req;
378 }
379
380 // This will need a new way to tell if it's hooked up to a cache or not.
381 if (req->isUncacheable())
382 recordEvent("Uncached Write");
383
384 // If the write needs to have a fault on the access, consider calling
385 // changeStatus() and changing it to "bad addr write" or something.

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452 _status = IcacheRetry;
453 } else {
454 // Need to wait for cache to respond
455 _status = IcacheWaitResponse;
456 // ownership of packet transferred to memory system
457 ifetch_pkt = NULL;
458 }
459 } else {
382 }
383
384 // This will need a new way to tell if it's hooked up to a cache or not.
385 if (req->isUncacheable())
386 recordEvent("Uncached Write");
387
388 // If the write needs to have a fault on the access, consider calling
389 // changeStatus() and changing it to "bad addr write" or something.

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456 _status = IcacheRetry;
457 } else {
458 // Need to wait for cache to respond
459 _status = IcacheWaitResponse;
460 // ownership of packet transferred to memory system
461 ifetch_pkt = NULL;
462 }
463 } else {
464 delete ifetch_req;
465 delete ifetch_pkt;
460 // fetch fault: advance directly to next instruction (fault handler)
461 advanceInst(fault);
462 }
463
464 numCycles += curTick - previousTick;
465 previousTick = curTick;
466}
467

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485{
486 // received a response from the icache: execute the received
487 // instruction
488 assert(pkt->result == Packet::Success);
489 assert(_status == IcacheWaitResponse);
490
491 _status = Running;
492
466 // fetch fault: advance directly to next instruction (fault handler)
467 advanceInst(fault);
468 }
469
470 numCycles += curTick - previousTick;
471 previousTick = curTick;
472}
473

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491{
492 // received a response from the icache: execute the received
493 // instruction
494 assert(pkt->result == Packet::Success);
495 assert(_status == IcacheWaitResponse);
496
497 _status = Running;
498
493 delete pkt->req;
494 delete pkt;
495
496 numCycles += curTick - previousTick;
497 previousTick = curTick;
498
499 if (getState() == SimObject::Draining) {
499 numCycles += curTick - previousTick;
500 previousTick = curTick;
501
502 if (getState() == SimObject::Draining) {
503 delete pkt->req;
504 delete pkt;
505
500 completeDrain();
501 return;
502 }
503
504 preExecute();
505 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
506 // load or store: just send to dcache
507 Fault fault = curStaticInst->initiateAcc(this, traceData);

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523 advanceInst(fault);
524 }
525 } else {
526 // non-memory instruction: execute completely now
527 Fault fault = curStaticInst->execute(this, traceData);
528 postExecute();
529 advanceInst(fault);
530 }
506 completeDrain();
507 return;
508 }
509
510 preExecute();
511 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
512 // load or store: just send to dcache
513 Fault fault = curStaticInst->initiateAcc(this, traceData);

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529 advanceInst(fault);
530 }
531 } else {
532 // non-memory instruction: execute completely now
533 Fault fault = curStaticInst->execute(this, traceData);
534 postExecute();
535 advanceInst(fault);
536 }
537
538 delete pkt->req;
539 delete pkt;
531}
532
533void
534TimingSimpleCPU::IcachePort::ITickEvent::process()
535{
536 cpu->completeIfetch(pkt);
537}
538

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541
542void
543TimingSimpleCPU::IcachePort::ITickEvent::process()
544{
545 cpu->completeIfetch(pkt);
546}
547

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