timing.cc (3647:8121d4503cbc) | timing.cc (3658:f0a7030c6bd9) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 68 unchanged lines hidden (view full) --- 77{ 78 //No internal storage to update, jusst return 79 return; 80} 81 82void 83TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 84{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 68 unchanged lines hidden (view full) --- 77{ 78 //No internal storage to update, jusst return 79 return; 80} 81 82void 83TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 84{ |
85 if (status == RangeChange) { 86 if (!snoopRangeSent) { 87 snoopRangeSent = true; 88 sendStatusChange(Port::RangeChange); 89 } | 85 if (status == RangeChange) |
90 return; | 86 return; |
91 } | |
92 93 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 94} 95 96 97void 98TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 99{ 100 pkt = _pkt; 101 Event::schedule(t); 102} 103 104TimingSimpleCPU::TimingSimpleCPU(Params *p) 105 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 106 cpu_id(p->cpu_id) 107{ 108 _status = Idle; | 87 88 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 89} 90 91 92void 93TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 94{ 95 pkt = _pkt; 96 Event::schedule(t); 97} 98 99TimingSimpleCPU::TimingSimpleCPU(Params *p) 100 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 101 cpu_id(p->cpu_id) 102{ 103 _status = Idle; |
109 110 icachePort.snoopRangeSent = false; 111 dcachePort.snoopRangeSent = false; 112 | |
113 ifetch_pkt = dcache_pkt = NULL; 114 drainEvent = NULL; 115 fetchEvent = NULL; 116 previousTick = 0; 117 changeState(SimObject::Running); 118} 119 120 --- 164 unchanged lines hidden (view full) --- 285 if (!dcachePort.sendTiming(pkt)) { 286 _status = DcacheRetry; 287 dcache_pkt = pkt; 288 } else { 289 _status = DcacheWaitResponse; 290 // memory system takes ownership of packet 291 dcache_pkt = NULL; 292 } | 104 ifetch_pkt = dcache_pkt = NULL; 105 drainEvent = NULL; 106 fetchEvent = NULL; 107 previousTick = 0; 108 changeState(SimObject::Running); 109} 110 111 --- 164 unchanged lines hidden (view full) --- 276 if (!dcachePort.sendTiming(pkt)) { 277 _status = DcacheRetry; 278 dcache_pkt = pkt; 279 } else { 280 _status = DcacheWaitResponse; 281 // memory system takes ownership of packet 282 dcache_pkt = NULL; 283 } |
284 } else { 285 delete req; |
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293 } 294 295 // This will need a new way to tell if it has a dcache attached. 296 if (req->isUncacheable()) 297 recordEvent("Uncached Read"); 298 299 return fault; 300} --- 69 unchanged lines hidden (view full) --- 370 if (!dcachePort.sendTiming(dcache_pkt)) { 371 _status = DcacheRetry; 372 } else { 373 _status = DcacheWaitResponse; 374 // memory system takes ownership of packet 375 dcache_pkt = NULL; 376 } 377 } | 286 } 287 288 // This will need a new way to tell if it has a dcache attached. 289 if (req->isUncacheable()) 290 recordEvent("Uncached Read"); 291 292 return fault; 293} --- 69 unchanged lines hidden (view full) --- 363 if (!dcachePort.sendTiming(dcache_pkt)) { 364 _status = DcacheRetry; 365 } else { 366 _status = DcacheWaitResponse; 367 // memory system takes ownership of packet 368 dcache_pkt = NULL; 369 } 370 } |
371 } else { 372 delete req; |
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378 } 379 380 // This will need a new way to tell if it's hooked up to a cache or not. 381 if (req->isUncacheable()) 382 recordEvent("Uncached Write"); 383 384 // If the write needs to have a fault on the access, consider calling 385 // changeStatus() and changing it to "bad addr write" or something. --- 66 unchanged lines hidden (view full) --- 452 _status = IcacheRetry; 453 } else { 454 // Need to wait for cache to respond 455 _status = IcacheWaitResponse; 456 // ownership of packet transferred to memory system 457 ifetch_pkt = NULL; 458 } 459 } else { | 373 } 374 375 // This will need a new way to tell if it's hooked up to a cache or not. 376 if (req->isUncacheable()) 377 recordEvent("Uncached Write"); 378 379 // If the write needs to have a fault on the access, consider calling 380 // changeStatus() and changing it to "bad addr write" or something. --- 66 unchanged lines hidden (view full) --- 447 _status = IcacheRetry; 448 } else { 449 // Need to wait for cache to respond 450 _status = IcacheWaitResponse; 451 // ownership of packet transferred to memory system 452 ifetch_pkt = NULL; 453 } 454 } else { |
455 delete ifetch_req; 456 delete ifetch_pkt; |
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460 // fetch fault: advance directly to next instruction (fault handler) 461 advanceInst(fault); 462 } 463 464 numCycles += curTick - previousTick; 465 previousTick = curTick; 466} 467 --- 17 unchanged lines hidden (view full) --- 485{ 486 // received a response from the icache: execute the received 487 // instruction 488 assert(pkt->result == Packet::Success); 489 assert(_status == IcacheWaitResponse); 490 491 _status = Running; 492 | 457 // fetch fault: advance directly to next instruction (fault handler) 458 advanceInst(fault); 459 } 460 461 numCycles += curTick - previousTick; 462 previousTick = curTick; 463} 464 --- 17 unchanged lines hidden (view full) --- 482{ 483 // received a response from the icache: execute the received 484 // instruction 485 assert(pkt->result == Packet::Success); 486 assert(_status == IcacheWaitResponse); 487 488 _status = Running; 489 |
493 delete pkt->req; 494 delete pkt; 495 | |
496 numCycles += curTick - previousTick; 497 previousTick = curTick; 498 499 if (getState() == SimObject::Draining) { | 490 numCycles += curTick - previousTick; 491 previousTick = curTick; 492 493 if (getState() == SimObject::Draining) { |
494 delete pkt->req; 495 delete pkt; 496 |
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500 completeDrain(); 501 return; 502 } 503 504 preExecute(); 505 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 506 // load or store: just send to dcache 507 Fault fault = curStaticInst->initiateAcc(this, traceData); --- 15 unchanged lines hidden (view full) --- 523 advanceInst(fault); 524 } 525 } else { 526 // non-memory instruction: execute completely now 527 Fault fault = curStaticInst->execute(this, traceData); 528 postExecute(); 529 advanceInst(fault); 530 } | 497 completeDrain(); 498 return; 499 } 500 501 preExecute(); 502 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 503 // load or store: just send to dcache 504 Fault fault = curStaticInst->initiateAcc(this, traceData); --- 15 unchanged lines hidden (view full) --- 520 advanceInst(fault); 521 } 522 } else { 523 // non-memory instruction: execute completely now 524 Fault fault = curStaticInst->execute(this, traceData); 525 postExecute(); 526 advanceInst(fault); 527 } |
528 529 delete pkt->req; 530 delete pkt; |
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531} 532 533void 534TimingSimpleCPU::IcachePort::ITickEvent::process() 535{ 536 cpu->completeIfetch(pkt); 537} 538 --- 225 unchanged lines hidden --- | 531} 532 533void 534TimingSimpleCPU::IcachePort::ITickEvent::process() 535{ 536 cpu->completeIfetch(pkt); 537} 538 --- 225 unchanged lines hidden --- |