timing.cc (3617:384e3b1eae06) timing.cc (3647:8121d4503cbc)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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77{
78 //No internal storage to update, jusst return
79 return;
80}
81
82void
83TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
84{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 68 unchanged lines hidden (view full) ---

77{
78 //No internal storage to update, jusst return
79 return;
80}
81
82void
83TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
84{
85 if (status == RangeChange)
85 if (status == RangeChange) {
86 if (!snoopRangeSent) {
87 snoopRangeSent = true;
88 sendStatusChange(Port::RangeChange);
89 }
86 return;
90 return;
91 }
87
88 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
89}
90
91
92void
93TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
94{
95 pkt = _pkt;
96 Event::schedule(t);
97}
98
99TimingSimpleCPU::TimingSimpleCPU(Params *p)
100 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
101 cpu_id(p->cpu_id)
102{
103 _status = Idle;
92
93 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
94}
95
96
97void
98TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
99{
100 pkt = _pkt;
101 Event::schedule(t);
102}
103
104TimingSimpleCPU::TimingSimpleCPU(Params *p)
105 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
106 cpu_id(p->cpu_id)
107{
108 _status = Idle;
109
110 icachePort.snoopRangeSent = false;
111 dcachePort.snoopRangeSent = false;
112
104 ifetch_pkt = dcache_pkt = NULL;
105 drainEvent = NULL;
106 fetchEvent = NULL;
107 previousTick = 0;
108 changeState(SimObject::Running);
109}
110
111

--- 643 unchanged lines hidden --- 		113 ifetch_pkt = dcache_pkt = NULL;
114 drainEvent = NULL;
115 fetchEvent = NULL;
116 previousTick = 0;
117 changeState(SimObject::Running);
118}
119
120

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