timing.cc (3495:884bf1f0c0c9) timing.cc (3617:384e3b1eae06)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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660 Param<Tick> progress_interval;
661 SimObjectParam<System *> system;
662 Param<int> cpu_id;
663
664#if FULL_SYSTEM
665 SimObjectParam<TheISA::ITB *> itb;
666 SimObjectParam<TheISA::DTB *> dtb;
667 Param<Tick> profile;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 651 unchanged lines hidden (view full) ---

660 Param<Tick> progress_interval;
661 SimObjectParam<System *> system;
662 Param<int> cpu_id;
663
664#if FULL_SYSTEM
665 SimObjectParam<TheISA::ITB *> itb;
666 SimObjectParam<TheISA::DTB *> dtb;
667 Param<Tick> profile;
668
669 Param<bool> do_quiesce;
670 Param<bool> do_checkpoint_insts;
671 Param<bool> do_statistics_insts;
668#else
669 SimObjectParam<Process *> workload;
670#endif // FULL_SYSTEM
671
672 Param<int> clock;
673
674 Param<bool> defer_registration;
675 Param<int> width;

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692 INIT_PARAM(progress_interval, "Progress interval"),
693 INIT_PARAM(system, "system object"),
694 INIT_PARAM(cpu_id, "processor ID"),
695
696#if FULL_SYSTEM
697 INIT_PARAM(itb, "Instruction TLB"),
698 INIT_PARAM(dtb, "Data TLB"),
699 INIT_PARAM(profile, ""),
672#else
673 SimObjectParam<Process *> workload;
674#endif // FULL_SYSTEM
675
676 Param<int> clock;
677
678 Param<bool> defer_registration;
679 Param<int> width;

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696 INIT_PARAM(progress_interval, "Progress interval"),
697 INIT_PARAM(system, "system object"),
698 INIT_PARAM(cpu_id, "processor ID"),
699
700#if FULL_SYSTEM
701 INIT_PARAM(itb, "Instruction TLB"),
702 INIT_PARAM(dtb, "Data TLB"),
703 INIT_PARAM(profile, ""),
704 INIT_PARAM(do_quiesce, ""),
705 INIT_PARAM(do_checkpoint_insts, ""),
706 INIT_PARAM(do_statistics_insts, ""),
700#else
701 INIT_PARAM(workload, "processes to run"),
702#endif // FULL_SYSTEM
703
704 INIT_PARAM(clock, "clock speed"),
705 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
706 INIT_PARAM(width, "cpu width"),
707 INIT_PARAM(function_trace, "Enable function trace"),

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727 params->functionTraceStart = function_trace_start;
728 params->system = system;
729 params->cpu_id = cpu_id;
730
731#if FULL_SYSTEM
732 params->itb = itb;
733 params->dtb = dtb;
734 params->profile = profile;
707#else
708 INIT_PARAM(workload, "processes to run"),
709#endif // FULL_SYSTEM
710
711 INIT_PARAM(clock, "clock speed"),
712 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
713 INIT_PARAM(width, "cpu width"),
714 INIT_PARAM(function_trace, "Enable function trace"),

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734 params->functionTraceStart = function_trace_start;
735 params->system = system;
736 params->cpu_id = cpu_id;
737
738#if FULL_SYSTEM
739 params->itb = itb;
740 params->dtb = dtb;
741 params->profile = profile;
742 params->do_quiesce = do_quiesce;
743 params->do_checkpoint_insts = do_checkpoint_insts;
744 params->do_statistics_insts = do_statistics_insts;
735#else
736 params->process = workload;
737#endif
738
739 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
740 return cpu;
741}
742
743REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
744
745#else
746 params->process = workload;
747#endif
748
749 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
750 return cpu;
751}
752
753REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
754