timing.cc (3479:4fbcaa81d105) | timing.cc (3495:884bf1f0c0c9) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 518 unchanged lines hidden (view full) --- 527 cpu->completeIfetch(pkt); 528} 529 530bool 531TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 532{ 533 if (pkt->isResponse()) { 534 // delay processing of returned data until next CPU clock edge | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 518 unchanged lines hidden (view full) --- 527 cpu->completeIfetch(pkt); 528} 529 530bool 531TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 532{ 533 if (pkt->isResponse()) { 534 // delay processing of returned data until next CPU clock edge |
535 Tick time = pkt->req->getTime(); 536 while (time < curTick) 537 time += lat; | 535 Tick mem_time = pkt->req->getTime(); 536 Tick next_tick = cpu->nextCycle(mem_time); |
538 | 537 |
539 if (time == curTick) | 538 if (next_tick == curTick) |
540 cpu->completeIfetch(pkt); 541 else | 539 cpu->completeIfetch(pkt); 540 else |
542 tickEvent.schedule(pkt, time); | 541 tickEvent.schedule(pkt, next_tick); |
543 544 return true; 545 } 546 else { 547 //Snooping a Coherence Request, do nothing 548 return true; 549 } 550} --- 54 unchanged lines hidden (view full) --- 605 drainEvent->process(); 606} 607 608bool 609TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 610{ 611 if (pkt->isResponse()) { 612 // delay processing of returned data until next CPU clock edge | 542 543 return true; 544 } 545 else { 546 //Snooping a Coherence Request, do nothing 547 return true; 548 } 549} --- 54 unchanged lines hidden (view full) --- 604 drainEvent->process(); 605} 606 607bool 608TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 609{ 610 if (pkt->isResponse()) { 611 // delay processing of returned data until next CPU clock edge |
613 Tick time = pkt->req->getTime(); 614 while (time < curTick) 615 time += lat; | 612 Tick mem_time = pkt->req->getTime(); 613 Tick next_tick = cpu->nextCycle(mem_time); |
616 | 614 |
617 if (time == curTick) | 615 if (next_tick == curTick) |
618 cpu->completeDataAccess(pkt); 619 else | 616 cpu->completeDataAccess(pkt); 617 else |
620 tickEvent.schedule(pkt, time); | 618 tickEvent.schedule(pkt, next_tick); |
621 622 return true; 623 } 624 else { 625 //Snooping a coherence req, do nothing 626 return true; 627 } 628} --- 118 unchanged lines hidden --- | 619 620 return true; 621 } 622 else { 623 //Snooping a coherence req, do nothing 624 return true; 625 } 626} --- 118 unchanged lines hidden --- |