timing.cc (3297:f0855ab36ff5) timing.cc (3310:21adbb41a37e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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523TimingSimpleCPU::IcachePort::ITickEvent::process()
524{
525 cpu->completeIfetch(pkt);
526}
527
528bool
529TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
530{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 514 unchanged lines hidden (view full) ---

523TimingSimpleCPU::IcachePort::ITickEvent::process()
524{
525 cpu->completeIfetch(pkt);
526}
527
528bool
529TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
530{
531 // delay processing of returned data until next CPU clock edge
532 Tick time = pkt->req->getTime();
533 while (time < curTick)
534 time += lat;
531 if (pkt->isResponse()) {
532 // delay processing of returned data until next CPU clock edge
533 Tick time = pkt->req->getTime();
534 while (time < curTick)
535 time += lat;
535
536
536 if (time == curTick)
537 cpu->completeIfetch(pkt);
538 else
539 tickEvent.schedule(pkt, time);
537 if (time == curTick)
538 cpu->completeIfetch(pkt);
539 else
540 tickEvent.schedule(pkt, time);
540
541
541 return true;
542 return true;
543 }
544 else {
545 //Snooping a Coherence Request, do nothing
546 return true;
547 }
542}
543
544void
545TimingSimpleCPU::IcachePort::recvRetry()
546{
547 // we shouldn't get a retry unless we have a packet that we're
548 // waiting to transmit
549 assert(cpu->ifetch_pkt != NULL);

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595 DPRINTF(Config, "Done draining\n");
596 changeState(SimObject::Drained);
597 drainEvent->process();
598}
599
600bool
601TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
602{
548}
549
550void
551TimingSimpleCPU::IcachePort::recvRetry()
552{
553 // we shouldn't get a retry unless we have a packet that we're
554 // waiting to transmit
555 assert(cpu->ifetch_pkt != NULL);

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601 DPRINTF(Config, "Done draining\n");
602 changeState(SimObject::Drained);
603 drainEvent->process();
604}
605
606bool
607TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
608{
603 // delay processing of returned data until next CPU clock edge
604 Tick time = pkt->req->getTime();
605 while (time < curTick)
606 time += lat;
609 if (pkt->isResponse()) {
610 // delay processing of returned data until next CPU clock edge
611 Tick time = pkt->req->getTime();
612 while (time < curTick)
613 time += lat;
607
614
608 if (time == curTick)
609 cpu->completeDataAccess(pkt);
610 else
611 tickEvent.schedule(pkt, time);
615 if (time == curTick)
616 cpu->completeDataAccess(pkt);
617 else
618 tickEvent.schedule(pkt, time);
612
619
613 return true;
620 return true;
621 }
622 else {
623 //Snooping a coherence req, do nothing
624 return true;
625 }
614}
615
616void
617TimingSimpleCPU::DcachePort::DTickEvent::process()
618{
619 cpu->completeDataAccess(pkt);
620}
621

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627
628void
629TimingSimpleCPU::DcachePort::DTickEvent::process()
630{
631 cpu->completeDataAccess(pkt);
632}
633

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