timing.cc (3201:7c3b18c01b0e) timing.cc (3222:19bd4dd3be83)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/timing.hh"
35#include "mem/packet_impl.hh"
36#include "sim/builder.hh"
37#include "sim/system.hh"
38
39using namespace std;

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69{
70 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
71 return curTick;
72}
73
74void
75TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
76{
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;

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68{
69 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
70 return curTick;
71}
72
73void
74TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
75{
77 //No internal storage to update, jusst return
78 return;
76 panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
79}
80
81void
82TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
83{
84 if (status == RangeChange)
85 return;
86

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91void
92TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
93{
94 pkt = _pkt;
95 Event::schedule(t);
96}
97
98TimingSimpleCPU::TimingSimpleCPU(Params *p)
77}
78
79void
80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84

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89void
90TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
91{
92 pkt = _pkt;
93 Event::schedule(t);
94}
95
96TimingSimpleCPU::TimingSimpleCPU(Params *p)
99 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
100 cpu_id(p->cpu_id)
97 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
101{
102 _status = Idle;
103 ifetch_pkt = dcache_pkt = NULL;
104 drainEvent = NULL;
105 fetchEvent = NULL;
98{
99 _status = Idle;
100 ifetch_pkt = dcache_pkt = NULL;
101 drainEvent = NULL;
102 fetchEvent = NULL;
103 previousTick = 0;
106 changeState(SimObject::Running);
107}
108
109
110TimingSimpleCPU::~TimingSimpleCPU()
111{
112}
113

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141 return 1;
142 }
143}
144
145void
146TimingSimpleCPU::resume()
147{
148 if (_status != SwitchedOut && _status != Idle) {
104 changeState(SimObject::Running);
105}
106
107
108TimingSimpleCPU::~TimingSimpleCPU()
109{
110}
111

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139 return 1;
140 }
141}
142
143void
144TimingSimpleCPU::resume()
145{
146 if (_status != SwitchedOut && _status != Idle) {
149 assert(system->getMemoryMode() == System::Timing);
150
151 // Delete the old event if it existed.
152 if (fetchEvent) {
153 if (fetchEvent->scheduled())
154 fetchEvent->deschedule();
155
156 delete fetchEvent;
157 }
158
159 fetchEvent =
160 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
161 fetchEvent->schedule(curTick);
162 }
163
147 // Delete the old event if it existed.
148 if (fetchEvent) {
149 if (fetchEvent->scheduled())
150 fetchEvent->deschedule();
151
152 delete fetchEvent;
153 }
154
155 fetchEvent =
156 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
157 fetchEvent->schedule(curTick);
158 }
159
160 assert(system->getMemoryMode() == System::Timing);
164 changeState(SimObject::Running);
161 changeState(SimObject::Running);
162 previousTick = curTick;
165}
166
167void
168TimingSimpleCPU::switchOut()
169{
170 assert(status() == Running || status() == Idle);
171 _status = SwitchedOut;
163}
164
165void
166TimingSimpleCPU::switchOut()
167{
168 assert(status() == Running || status() == Idle);
169 _status = SwitchedOut;
170 numCycles += curTick - previousTick;
172
173 // If we've been scheduled to resume but are then told to switch out,
174 // we'll need to cancel it.
175 if (fetchEvent && fetchEvent->scheduled())
176 fetchEvent->deschedule();
177}
178
179

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187 for (int i = 0; i < threadContexts.size(); ++i) {
188 ThreadContext *tc = threadContexts[i];
189 if (tc->status() == ThreadContext::Active && _status != Running) {
190 _status = Running;
191 break;
192 }
193 }
194
171
172 // If we've been scheduled to resume but are then told to switch out,
173 // we'll need to cancel it.
174 if (fetchEvent && fetchEvent->scheduled())
175 fetchEvent->deschedule();
176}
177
178

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186 for (int i = 0; i < threadContexts.size(); ++i) {
187 ThreadContext *tc = threadContexts[i];
188 if (tc->status() == ThreadContext::Active && _status != Running) {
189 _status = Running;
190 break;
191 }
192 }
193
195 if (_status != Running) {
196 _status = Idle;
194 Port *peer;
195 if (icachePort.getPeer() == NULL) {
196 peer = oldCPU->getPort("icachePort")->getPeer();
197 icachePort.setPeer(peer);
198 } else {
199 peer = icachePort.getPeer();
197 }
200 }
201 peer->setPeer(&icachePort);
202
203 if (dcachePort.getPeer() == NULL) {
204 peer = oldCPU->getPort("dcachePort")->getPeer();
205 dcachePort.setPeer(peer);
206 } else {
207 peer = dcachePort.getPeer();
208 }
209 peer->setPeer(&dcachePort);
198}
199
200
201void
202TimingSimpleCPU::activateContext(int thread_num, int delay)
203{
204 assert(thread_num == 0);
205 assert(thread);

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230 _status = Idle;
231}
232
233
234template <class T>
235Fault
236TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
237{
210}
211
212
213void
214TimingSimpleCPU::activateContext(int thread_num, int delay)
215{
216 assert(thread_num == 0);
217 assert(thread);

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242 _status = Idle;
243}
244
245
246template <class T>
247Fault
248TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
249{
238 Request *req =
239 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
240 cpu_id, /* thread ID */ 0);
250 // need to fill in CPU & thread IDs here
251 Request *data_read_req = new Request();
252 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
253 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
241
242 if (traceData) {
254
255 if (traceData) {
243 traceData->setAddr(req->getVaddr());
256 traceData->setAddr(data_read_req->getVaddr());
244 }
245
246 // translate to physical address
257 }
258
259 // translate to physical address
247 Fault fault = thread->translateDataReadReq(req);
260 Fault fault = thread->translateDataReadReq(data_read_req);
248
249 // Now do the access.
250 if (fault == NoFault) {
261
262 // Now do the access.
263 if (fault == NoFault) {
251 Packet *pkt =
252 new Packet(req, Packet::ReadReq, Packet::Broadcast);
253 pkt->dataDynamic(new T);
264 Packet *data_read_pkt =
265 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
266 data_read_pkt->dataDynamic<T>(new T);
254
267
255 if (!dcachePort.sendTiming(pkt)) {
268 if (!dcachePort.sendTiming(data_read_pkt)) {
256 _status = DcacheRetry;
269 _status = DcacheRetry;
257 dcache_pkt = pkt;
270 dcache_pkt = data_read_pkt;
258 } else {
259 _status = DcacheWaitResponse;
271 } else {
272 _status = DcacheWaitResponse;
260 // memory system takes ownership of packet
261 dcache_pkt = NULL;
262 }
263 }
264
265 // This will need a new way to tell if it has a dcache attached.
273 dcache_pkt = NULL;
274 }
275 }
276
277 // This will need a new way to tell if it has a dcache attached.
266 if (req->isUncacheable())
278 if (data_read_req->getFlags() & UNCACHEABLE)
267 recordEvent("Uncached Read");
268
269 return fault;
270}
271
272#ifndef DOXYGEN_SHOULD_SKIP_THIS
273
274template

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311 return read(addr, (uint32_t&)data, flags);
312}
313
314
315template <class T>
316Fault
317TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
318{
279 recordEvent("Uncached Read");
280
281 return fault;
282}
283
284#ifndef DOXYGEN_SHOULD_SKIP_THIS
285
286template

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323 return read(addr, (uint32_t&)data, flags);
324}
325
326
327template <class T>
328Fault
329TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
330{
319 Request *req =
320 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
321 cpu_id, /* thread ID */ 0);
331 // need to fill in CPU & thread IDs here
332 Request *data_write_req = new Request();
333 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
334 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
322
323 // translate to physical address
335
336 // translate to physical address
324 Fault fault = thread->translateDataWriteReq(req);
325
337 Fault fault = thread->translateDataWriteReq(data_write_req);
326 // Now do the access.
327 if (fault == NoFault) {
338 // Now do the access.
339 if (fault == NoFault) {
328 assert(dcache_pkt == NULL);
329 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
330 dcache_pkt->allocate();
331 dcache_pkt->set(data);
340 Packet *data_write_pkt =
341 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
342 data_write_pkt->allocate();
343 data_write_pkt->set(data);
332
344
333 bool do_access = true; // flag to suppress cache access
334
335 if (req->isLocked()) {
336 do_access = TheISA::handleLockedWrite(thread, req);
345 if (!dcachePort.sendTiming(data_write_pkt)) {
346 _status = DcacheRetry;
347 dcache_pkt = data_write_pkt;
348 } else {
349 _status = DcacheWaitResponse;
350 dcache_pkt = NULL;
337 }
351 }
338
339 if (do_access) {
340 if (!dcachePort.sendTiming(dcache_pkt)) {
341 _status = DcacheRetry;
342 } else {
343 _status = DcacheWaitResponse;
344 // memory system takes ownership of packet
345 dcache_pkt = NULL;
346 }
347 }
348 }
349
350 // This will need a new way to tell if it's hooked up to a cache or not.
352 }
353
354 // This will need a new way to tell if it's hooked up to a cache or not.
351 if (req->isUncacheable())
355 if (data_write_req->getFlags() & UNCACHEABLE)
352 recordEvent("Uncached Write");
353
354 // If the write needs to have a fault on the access, consider calling
355 // changeStatus() and changing it to "bad addr write" or something.
356 return fault;
357}
358
359

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403}
404
405
406void
407TimingSimpleCPU::fetch()
408{
409 checkForInterrupts();
410
356 recordEvent("Uncached Write");
357
358 // If the write needs to have a fault on the access, consider calling
359 // changeStatus() and changing it to "bad addr write" or something.
360 return fault;
361}
362
363

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407}
408
409
410void
411TimingSimpleCPU::fetch()
412{
413 checkForInterrupts();
414
415 // need to fill in CPU & thread IDs here
411 Request *ifetch_req = new Request();
416 Request *ifetch_req = new Request();
412 ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
417 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
413 Fault fault = setupFetchRequest(ifetch_req);
414
415 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
416 ifetch_pkt->dataStatic(&inst);
417
418 if (fault == NoFault) {
419 if (!icachePort.sendTiming(ifetch_pkt)) {
420 // Need to wait for retry
421 _status = IcacheRetry;
422 } else {
423 // Need to wait for cache to respond
424 _status = IcacheWaitResponse;
425 // ownership of packet transferred to memory system
426 ifetch_pkt = NULL;
427 }
428 } else {
429 // fetch fault: advance directly to next instruction (fault handler)
430 advanceInst(fault);
431 }
418 Fault fault = setupFetchRequest(ifetch_req);
419
420 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
421 ifetch_pkt->dataStatic(&inst);
422
423 if (fault == NoFault) {
424 if (!icachePort.sendTiming(ifetch_pkt)) {
425 // Need to wait for retry
426 _status = IcacheRetry;
427 } else {
428 // Need to wait for cache to respond
429 _status = IcacheWaitResponse;
430 // ownership of packet transferred to memory system
431 ifetch_pkt = NULL;
432 }
433 } else {
434 // fetch fault: advance directly to next instruction (fault handler)
435 advanceInst(fault);
436 }
437
438 numCycles += curTick - previousTick;
439 previousTick = curTick;
432}
433
434
435void
436TimingSimpleCPU::advanceInst(Fault fault)
437{
438 advancePC(fault);
439

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454 assert(pkt->result == Packet::Success);
455 assert(_status == IcacheWaitResponse);
456
457 _status = Running;
458
459 delete pkt->req;
460 delete pkt;
461
440}
441
442
443void
444TimingSimpleCPU::advanceInst(Fault fault)
445{
446 advancePC(fault);
447

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462 assert(pkt->result == Packet::Success);
463 assert(_status == IcacheWaitResponse);
464
465 _status = Running;
466
467 delete pkt->req;
468 delete pkt;
469
470 numCycles += curTick - previousTick;
471 previousTick = curTick;
472
462 if (getState() == SimObject::Draining) {
463 completeDrain();
464 return;
465 }
466
467 preExecute();
468 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
469 // load or store: just send to dcache
470 Fault fault = curStaticInst->initiateAcc(this, traceData);
473 if (getState() == SimObject::Draining) {
474 completeDrain();
475 return;
476 }
477
478 preExecute();
479 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
480 // load or store: just send to dcache
481 Fault fault = curStaticInst->initiateAcc(this, traceData);
471 if (_status != Running) {
472 // instruction will complete in dcache response callback
473 assert(_status == DcacheWaitResponse || _status == DcacheRetry);
474 assert(fault == NoFault);
482 if (fault == NoFault) {
483 // successfully initiated access: instruction will
484 // complete in dcache response callback
485 assert(_status == DcacheWaitResponse);
475 } else {
486 } else {
476 if (fault == NoFault) {
477 // early fail on store conditional: complete now
478 assert(dcache_pkt != NULL);
479 fault = curStaticInst->completeAcc(dcache_pkt, this,
480 traceData);
481 delete dcache_pkt->req;
482 delete dcache_pkt;
483 dcache_pkt = NULL;
484 }
487 // fault: complete now to invoke fault handler
485 postExecute();
486 advanceInst(fault);
487 }
488 } else {
489 // non-memory instruction: execute completely now
490 Fault fault = curStaticInst->execute(this, traceData);
491 postExecute();
492 advanceInst(fault);

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497TimingSimpleCPU::IcachePort::ITickEvent::process()
498{
499 cpu->completeIfetch(pkt);
500}
501
502bool
503TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
504{
488 postExecute();
489 advanceInst(fault);
490 }
491 } else {
492 // non-memory instruction: execute completely now
493 Fault fault = curStaticInst->execute(this, traceData);
494 postExecute();
495 advanceInst(fault);

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500TimingSimpleCPU::IcachePort::ITickEvent::process()
501{
502 cpu->completeIfetch(pkt);
503}
504
505bool
506TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
507{
505 // delay processing of returned data until next CPU clock edge
508 // These next few lines could be replaced with something faster
509 // who knows what though
506 Tick time = pkt->req->getTime();
507 while (time < curTick)
508 time += lat;
509
510 if (time == curTick)
511 cpu->completeIfetch(pkt);
512 else
513 tickEvent.schedule(pkt, time);

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533TimingSimpleCPU::completeDataAccess(Packet *pkt)
534{
535 // received a response from the dcache: complete the load or store
536 // instruction
537 assert(pkt->result == Packet::Success);
538 assert(_status == DcacheWaitResponse);
539 _status = Running;
540
510 Tick time = pkt->req->getTime();
511 while (time < curTick)
512 time += lat;
513
514 if (time == curTick)
515 cpu->completeIfetch(pkt);
516 else
517 tickEvent.schedule(pkt, time);

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537TimingSimpleCPU::completeDataAccess(Packet *pkt)
538{
539 // received a response from the dcache: complete the load or store
540 // instruction
541 assert(pkt->result == Packet::Success);
542 assert(_status == DcacheWaitResponse);
543 _status = Running;
544
541 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
545 numCycles += curTick - previousTick;
546 previousTick = curTick;
542
547
543 if (pkt->isRead() && pkt->req->isLocked()) {
544 TheISA::handleLockedRead(thread, pkt->req);
545 }
546
547 delete pkt->req;
548 delete pkt;
549
550 if (getState() == SimObject::Draining) {
548 if (getState() == SimObject::Draining) {
551 advancePC(fault);
552 completeDrain();
553
549 completeDrain();
550
551 delete pkt->req;
552 delete pkt;
553
554 return;
555 }
556
554 return;
555 }
556
557 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
558
559 delete pkt->req;
560 delete pkt;
561
557 postExecute();
558 advanceInst(fault);
559}
560
561
562void
563TimingSimpleCPU::completeDrain()
564{
565 DPRINTF(Config, "Done draining\n");
566 changeState(SimObject::Drained);
567 drainEvent->process();
568}
569
570bool
571TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
572{
562 postExecute();
563 advanceInst(fault);
564}
565
566
567void
568TimingSimpleCPU::completeDrain()
569{
570 DPRINTF(Config, "Done draining\n");
571 changeState(SimObject::Drained);
572 drainEvent->process();
573}
574
575bool
576TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
577{
573 // delay processing of returned data until next CPU clock edge
574 Tick time = pkt->req->getTime();
575 while (time < curTick)
576 time += lat;
577
578 if (time == curTick)
579 cpu->completeDataAccess(pkt);
580 else
581 tickEvent.schedule(pkt, time);

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594{
595 // we shouldn't get a retry unless we have a packet that we're
596 // waiting to transmit
597 assert(cpu->dcache_pkt != NULL);
598 assert(cpu->_status == DcacheRetry);
599 Packet *tmp = cpu->dcache_pkt;
600 if (sendTiming(tmp)) {
601 cpu->_status = DcacheWaitResponse;
578 Tick time = pkt->req->getTime();
579 while (time < curTick)
580 time += lat;
581
582 if (time == curTick)
583 cpu->completeDataAccess(pkt);
584 else
585 tickEvent.schedule(pkt, time);

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598{
599 // we shouldn't get a retry unless we have a packet that we're
600 // waiting to transmit
601 assert(cpu->dcache_pkt != NULL);
602 assert(cpu->_status == DcacheRetry);
603 Packet *tmp = cpu->dcache_pkt;
604 if (sendTiming(tmp)) {
605 cpu->_status = DcacheWaitResponse;
602 // memory system takes ownership of packet
603 cpu->dcache_pkt = NULL;
604 }
605}
606
607
608////////////////////////////////////////////////////////////////////////
609//
610// TimingSimpleCPU Simulation Object
611//
612BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
613
614 Param<Counter> max_insts_any_thread;
615 Param<Counter> max_insts_all_threads;
616 Param<Counter> max_loads_any_thread;
617 Param<Counter> max_loads_all_threads;
618 Param<Tick> progress_interval;
619 SimObjectParam<MemObject *> mem;
620 SimObjectParam<System *> system;
606 cpu->dcache_pkt = NULL;
607 }
608}
609
610
611////////////////////////////////////////////////////////////////////////
612//
613// TimingSimpleCPU Simulation Object
614//
615BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
616
617 Param<Counter> max_insts_any_thread;
618 Param<Counter> max_insts_all_threads;
619 Param<Counter> max_loads_any_thread;
620 Param<Counter> max_loads_all_threads;
621 Param<Tick> progress_interval;
622 SimObjectParam<MemObject *> mem;
623 SimObjectParam<System *> system;
621 Param<int> cpu_id;
622
623#if FULL_SYSTEM
624 SimObjectParam<AlphaITB *> itb;
625 SimObjectParam<AlphaDTB *> dtb;
624
625#if FULL_SYSTEM
626 SimObjectParam<AlphaITB *> itb;
627 SimObjectParam<AlphaDTB *> dtb;
628 Param<int> cpu_id;
626 Param<Tick> profile;
627#else
628 SimObjectParam<Process *> workload;
629#endif // FULL_SYSTEM
630
631 Param<int> clock;
632
633 Param<bool> defer_registration;

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646 "terminate when all threads have reached this inst count"),
647 INIT_PARAM(max_loads_any_thread,
648 "terminate when any thread reaches this load count"),
649 INIT_PARAM(max_loads_all_threads,
650 "terminate when all threads have reached this load count"),
651 INIT_PARAM(progress_interval, "Progress interval"),
652 INIT_PARAM(mem, "memory"),
653 INIT_PARAM(system, "system object"),
629 Param<Tick> profile;
630#else
631 SimObjectParam<Process *> workload;
632#endif // FULL_SYSTEM
633
634 Param<int> clock;
635
636 Param<bool> defer_registration;

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649 "terminate when all threads have reached this inst count"),
650 INIT_PARAM(max_loads_any_thread,
651 "terminate when any thread reaches this load count"),
652 INIT_PARAM(max_loads_all_threads,
653 "terminate when all threads have reached this load count"),
654 INIT_PARAM(progress_interval, "Progress interval"),
655 INIT_PARAM(mem, "memory"),
656 INIT_PARAM(system, "system object"),
654 INIT_PARAM(cpu_id, "processor ID"),
655
656#if FULL_SYSTEM
657 INIT_PARAM(itb, "Instruction TLB"),
658 INIT_PARAM(dtb, "Data TLB"),
657
658#if FULL_SYSTEM
659 INIT_PARAM(itb, "Instruction TLB"),
660 INIT_PARAM(dtb, "Data TLB"),
661 INIT_PARAM(cpu_id, "processor ID"),
659 INIT_PARAM(profile, ""),
660#else
661 INIT_PARAM(workload, "processes to run"),
662#endif // FULL_SYSTEM
663
664 INIT_PARAM(clock, "clock speed"),
665 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
666 INIT_PARAM(width, "cpu width"),

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682 params->max_loads_all_threads = max_loads_all_threads;
683 params->progress_interval = progress_interval;
684 params->deferRegistration = defer_registration;
685 params->clock = clock;
686 params->functionTrace = function_trace;
687 params->functionTraceStart = function_trace_start;
688 params->mem = mem;
689 params->system = system;
662 INIT_PARAM(profile, ""),
663#else
664 INIT_PARAM(workload, "processes to run"),
665#endif // FULL_SYSTEM
666
667 INIT_PARAM(clock, "clock speed"),
668 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
669 INIT_PARAM(width, "cpu width"),

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685 params->max_loads_all_threads = max_loads_all_threads;
686 params->progress_interval = progress_interval;
687 params->deferRegistration = defer_registration;
688 params->clock = clock;
689 params->functionTrace = function_trace;
690 params->functionTraceStart = function_trace_start;
691 params->mem = mem;
692 params->system = system;
690 params->cpu_id = cpu_id;
691
692#if FULL_SYSTEM
693 params->itb = itb;
694 params->dtb = dtb;
693
694#if FULL_SYSTEM
695 params->itb = itb;
696 params->dtb = dtb;
697 params->cpu_id = cpu_id;
695 params->profile = profile;
696#else
697 params->process = workload;
698#endif
699
700 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
701 return cpu;
702}
703
704REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
705
698 params->profile = profile;
699#else
700 params->process = workload;
701#endif
702
703 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
704 return cpu;
705}
706
707REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
708