timing.cc (3184:8edaf4539e05) timing.cc (3201:7c3b18c01b0e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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141 return 1;
142 }
143}
144
145void
146TimingSimpleCPU::resume()
147{
148 if (_status != SwitchedOut && _status != Idle) {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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141 return 1;
142 }
143}
144
145void
146TimingSimpleCPU::resume()
147{
148 if (_status != SwitchedOut && _status != Idle) {
149 assert(system->getMemoryMode() == System::Timing);
150
149 // Delete the old event if it existed.
150 if (fetchEvent) {
151 if (fetchEvent->scheduled())
152 fetchEvent->deschedule();
153
154 delete fetchEvent;
155 }
156
157 fetchEvent =
158 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
159 fetchEvent->schedule(curTick);
160 }
161
151 // Delete the old event if it existed.
152 if (fetchEvent) {
153 if (fetchEvent->scheduled())
154 fetchEvent->deschedule();
155
156 delete fetchEvent;
157 }
158
159 fetchEvent =
160 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
161 fetchEvent->schedule(curTick);
162 }
163
162 assert(system->getMemoryMode() == System::Timing);
163 changeState(SimObject::Running);
164}
165
166void
167TimingSimpleCPU::switchOut()
168{
169 assert(status() == Running || status() == Idle);
170 _status = SwitchedOut;

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185 // running and schedule its tick event.
186 for (int i = 0; i < threadContexts.size(); ++i) {
187 ThreadContext *tc = threadContexts[i];
188 if (tc->status() == ThreadContext::Active && _status != Running) {
189 _status = Running;
190 break;
191 }
192 }
164 changeState(SimObject::Running);
165}
166
167void
168TimingSimpleCPU::switchOut()
169{
170 assert(status() == Running || status() == Idle);
171 _status = SwitchedOut;

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186 // running and schedule its tick event.
187 for (int i = 0; i < threadContexts.size(); ++i) {
188 ThreadContext *tc = threadContexts[i];
189 if (tc->status() == ThreadContext::Active && _status != Running) {
190 _status = Running;
191 break;
192 }
193 }
194
195 if (_status != Running) {
196 _status = Idle;
197 }
193}
194
195
196void
197TimingSimpleCPU::activateContext(int thread_num, int delay)
198{
199 assert(thread_num == 0);
200 assert(thread);

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528TimingSimpleCPU::completeDataAccess(Packet *pkt)
529{
530 // received a response from the dcache: complete the load or store
531 // instruction
532 assert(pkt->result == Packet::Success);
533 assert(_status == DcacheWaitResponse);
534 _status = Running;
535
198}
199
200
201void
202TimingSimpleCPU::activateContext(int thread_num, int delay)
203{
204 assert(thread_num == 0);
205 assert(thread);

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533TimingSimpleCPU::completeDataAccess(Packet *pkt)
534{
535 // received a response from the dcache: complete the load or store
536 // instruction
537 assert(pkt->result == Packet::Success);
538 assert(_status == DcacheWaitResponse);
539 _status = Running;
540
536 if (getState() == SimObject::Draining) {
537 completeDrain();
538
539 delete pkt->req;
540 delete pkt;
541
542 return;
543 }
544
545 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
546
547 if (pkt->isRead() && pkt->req->isLocked()) {
548 TheISA::handleLockedRead(thread, pkt->req);
549 }
550
551 delete pkt->req;
552 delete pkt;
553
541 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
542
543 if (pkt->isRead() && pkt->req->isLocked()) {
544 TheISA::handleLockedRead(thread, pkt->req);
545 }
546
547 delete pkt->req;
548 delete pkt;
549
550 if (getState() == SimObject::Draining) {
551 advancePC(fault);
552 completeDrain();
553
554 return;
555 }
556
554 postExecute();
555 advanceInst(fault);
556}
557
558
559void
560TimingSimpleCPU::completeDrain()
561{

--- 141 unchanged lines hidden --- 		557 postExecute();
558 advanceInst(fault);
559}
560
561
562void
563TimingSimpleCPU::completeDrain()
564{

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