timing.cc (3119:6c93a7460ecf) timing.cc (3169:65bef767b5de)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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222 _status = Idle;
223}
224
225
226template <class T>
227Fault
228TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
229{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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222 _status = Idle;
223}
224
225
226template <class T>
227Fault
228TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
229{
230 // need to fill in CPU & thread IDs here
231 Request *data_read_req = new Request();
232 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
233 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
230 Request *req =
231 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
232 /* CPU ID */ 0, /* thread ID */ 0);
234
235 if (traceData) {
233
234 if (traceData) {
236 traceData->setAddr(data_read_req->getVaddr());
235 traceData->setAddr(req->getVaddr());
237 }
238
239 // translate to physical address
236 }
237
238 // translate to physical address
240 Fault fault = thread->translateDataReadReq(data_read_req);
239 Fault fault = thread->translateDataReadReq(req);
241
242 // Now do the access.
243 if (fault == NoFault) {
240
241 // Now do the access.
242 if (fault == NoFault) {
244 Packet *data_read_pkt =
245 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
246 data_read_pkt->dataDynamic<T>(new T);
243 Packet *pkt =
244 new Packet(req, Packet::ReadReq, Packet::Broadcast);
245 pkt->dataDynamic(new T);
247
246
248 if (!dcachePort.sendTiming(data_read_pkt)) {
247 if (!dcachePort.sendTiming(pkt)) {
249 _status = DcacheRetry;
248 _status = DcacheRetry;
250 dcache_pkt = data_read_pkt;
249 dcache_pkt = pkt;
251 } else {
252 _status = DcacheWaitResponse;
250 } else {
251 _status = DcacheWaitResponse;
252 // memory system takes ownership of packet
253 dcache_pkt = NULL;
254 }
255 }
256
257 // This will need a new way to tell if it has a dcache attached.
253 dcache_pkt = NULL;
254 }
255 }
256
257 // This will need a new way to tell if it has a dcache attached.
258 if (data_read_req->getFlags() & UNCACHEABLE)
258 if (req->getFlags() & UNCACHEABLE)
259 recordEvent("Uncached Read");
260
261 return fault;
262}
263
264#ifndef DOXYGEN_SHOULD_SKIP_THIS
265
266template

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303 return read(addr, (uint32_t&)data, flags);
304}
305
306
307template <class T>
308Fault
309TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
310{
259 recordEvent("Uncached Read");
260
261 return fault;
262}
263
264#ifndef DOXYGEN_SHOULD_SKIP_THIS
265
266template

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303 return read(addr, (uint32_t&)data, flags);
304}
305
306
307template <class T>
308Fault
309TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
310{
311 // need to fill in CPU & thread IDs here
312 Request *data_write_req = new Request();
313 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
314 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
311 Request *req =
312 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
313 /* CPU ID */ 0, /* thread ID */ 0);
315
316 // translate to physical address
314
315 // translate to physical address
317 Fault fault = thread->translateDataWriteReq(data_write_req);
316 Fault fault = thread->translateDataWriteReq(req);
317
318 // Now do the access.
319 if (fault == NoFault) {
318 // Now do the access.
319 if (fault == NoFault) {
320 Packet *data_write_pkt =
321 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
322 data_write_pkt->allocate();
323 data_write_pkt->set(data);
320 assert(dcache_pkt == NULL);
321 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
322 dcache_pkt->allocate();
323 dcache_pkt->set(data);
324
324
325 if (!dcachePort.sendTiming(data_write_pkt)) {
325 if (!dcachePort.sendTiming(dcache_pkt)) {
326 _status = DcacheRetry;
326 _status = DcacheRetry;
327 dcache_pkt = data_write_pkt;
328 } else {
329 _status = DcacheWaitResponse;
327 } else {
328 _status = DcacheWaitResponse;
329 // memory system takes ownership of packet
330 dcache_pkt = NULL;
331 }
332 }
333
334 // This will need a new way to tell if it's hooked up to a cache or not.
330 dcache_pkt = NULL;
331 }
332 }
333
334 // This will need a new way to tell if it's hooked up to a cache or not.
335 if (data_write_req->getFlags() & UNCACHEABLE)
335 if (req->getFlags() & UNCACHEABLE)
336 recordEvent("Uncached Write");
337
338 // If the write needs to have a fault on the access, consider calling
339 // changeStatus() and changing it to "bad addr write" or something.
340 return fault;
341}
342
343

--- 336 unchanged lines hidden --- 		336 recordEvent("Uncached Write");
337
338 // If the write needs to have a fault on the access, consider calling
339 // changeStatus() and changing it to "bad addr write" or something.
340 return fault;
341}
342
343

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