timing.cc (2923:db8a876258df) timing.cc (2948:ae26cf37957c)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
86}
87
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
86}
87
88
89void
90TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
91{
92 pkt = _pkt;
93 Event::schedule(t);
94}
95
88TimingSimpleCPU::TimingSimpleCPU(Params *p)
96TimingSimpleCPU::TimingSimpleCPU(Params *p)
89 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
97 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
90{
91 _status = Idle;
92 ifetch_pkt = dcache_pkt = NULL;
93 drainEvent = NULL;
94 fetchEvent = NULL;
95 changeState(SimObject::Running);
96}
97

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457 } else {
458 // non-memory instruction: execute completely now
459 Fault fault = curStaticInst->execute(this, traceData);
460 postExecute();
461 advanceInst(fault);
462 }
463}
464
98{
99 _status = Idle;
100 ifetch_pkt = dcache_pkt = NULL;
101 drainEvent = NULL;
102 fetchEvent = NULL;
103 changeState(SimObject::Running);
104}
105

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465 } else {
466 // non-memory instruction: execute completely now
467 Fault fault = curStaticInst->execute(this, traceData);
468 postExecute();
469 advanceInst(fault);
470 }
471}
472
473void
474TimingSimpleCPU::IcachePort::ITickEvent::process()
475{
476 cpu->completeIfetch(pkt);
477}
465
466bool
467TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
468{
478
479bool
480TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
481{
469 cpu->completeIfetch(pkt);
482 // These next few lines could be replaced with something faster
483 // who knows what though
484 Tick time = pkt->req->getTime();
485 while (time < curTick)
486 time += lat;
487
488 if (time == curTick)
489 cpu->completeIfetch(pkt);
490 else
491 tickEvent.schedule(pkt, time);
492
470 return true;
471}
472
473void
474TimingSimpleCPU::IcachePort::recvRetry()
475{
476 // we shouldn't get a retry unless we have a packet that we're
477 // waiting to transmit

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518 DPRINTF(Config, "Done draining\n");
519 changeState(SimObject::Drained);
520 drainEvent->process();
521}
522
523bool
524TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
525{
493 return true;
494}
495
496void
497TimingSimpleCPU::IcachePort::recvRetry()
498{
499 // we shouldn't get a retry unless we have a packet that we're
500 // waiting to transmit

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541 DPRINTF(Config, "Done draining\n");
542 changeState(SimObject::Drained);
543 drainEvent->process();
544}
545
546bool
547TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
548{
526 cpu->completeDataAccess(pkt);
549 Tick time = pkt->req->getTime();
550 while (time < curTick)
551 time += lat;
552
553 if (time == curTick)
554 cpu->completeDataAccess(pkt);
555 else
556 tickEvent.schedule(pkt, time);
557
527 return true;
528}
529
530void
558 return true;
559}
560
561void
562TimingSimpleCPU::DcachePort::DTickEvent::process()
563{
564 cpu->completeDataAccess(pkt);
565}
566
567void
531TimingSimpleCPU::DcachePort::recvRetry()
532{
533 // we shouldn't get a retry unless we have a packet that we're
534 // waiting to transmit
535 assert(cpu->dcache_pkt != NULL);
536 assert(cpu->_status == DcacheRetry);
537 Packet *tmp = cpu->dcache_pkt;
538 if (sendTiming(tmp)) {

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569{
570 // we shouldn't get a retry unless we have a packet that we're
571 // waiting to transmit
572 assert(cpu->dcache_pkt != NULL);
573 assert(cpu->_status == DcacheRetry);
574 Packet *tmp = cpu->dcache_pkt;
575 if (sendTiming(tmp)) {

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