timing.cc (2869:4dbf4770df29) | timing.cc (2901:f9a45473ab55) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" |
36#include "sim/system.hh" |
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36 37using namespace std; 38using namespace TheISA; 39 40Port * 41TimingSimpleCPU::getPort(const std::string &if_name, int idx) 42{ 43 if (if_name == "dcache_port") --- 42 unchanged lines hidden (view full) --- 86 87TimingSimpleCPU::TimingSimpleCPU(Params *p) 88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 89{ 90 _status = Idle; 91 ifetch_pkt = dcache_pkt = NULL; 92 drainEvent = NULL; 93 fetchEvent = NULL; | 37 38using namespace std; 39using namespace TheISA; 40 41Port * 42TimingSimpleCPU::getPort(const std::string &if_name, int idx) 43{ 44 if (if_name == "dcache_port") --- 42 unchanged lines hidden (view full) --- 87 88TimingSimpleCPU::TimingSimpleCPU(Params *p) 89 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 90{ 91 _status = Idle; 92 ifetch_pkt = dcache_pkt = NULL; 93 drainEvent = NULL; 94 fetchEvent = NULL; |
94 state = SimObject::Timing; | 95 changeState(SimObject::Running); |
95} 96 97 98TimingSimpleCPU::~TimingSimpleCPU() 99{ 100} 101 102void --- 5 unchanged lines hidden (view full) --- 108 109void 110TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 111{ 112 UNSERIALIZE_ENUM(_status); 113 BaseSimpleCPU::unserialize(cp, section); 114} 115 | 96} 97 98 99TimingSimpleCPU::~TimingSimpleCPU() 100{ 101} 102 103void --- 5 unchanged lines hidden (view full) --- 109 110void 111TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 112{ 113 UNSERIALIZE_ENUM(_status); 114 BaseSimpleCPU::unserialize(cp, section); 115} 116 |
116bool | 117unsigned int |
117TimingSimpleCPU::drain(Event *drain_event) 118{ 119 // TimingSimpleCPU is ready to drain if it's not waiting for 120 // an access to complete. 121 if (status() == Idle || status() == Running || status() == SwitchedOut) { | 118TimingSimpleCPU::drain(Event *drain_event) 119{ 120 // TimingSimpleCPU is ready to drain if it's not waiting for 121 // an access to complete. 122 if (status() == Idle || status() == Running || status() == SwitchedOut) { |
122 changeState(SimObject::DrainedTiming); 123 return true; | 123 changeState(SimObject::Drained); 124 return 0; |
124 } else { 125 changeState(SimObject::Draining); 126 drainEvent = drain_event; | 125 } else { 126 changeState(SimObject::Draining); 127 drainEvent = drain_event; |
127 return false; | 128 return 1; |
128 } 129} 130 131void 132TimingSimpleCPU::resume() 133{ 134 if (_status != SwitchedOut && _status != Idle) { 135 // Delete the old event if it existed. 136 if (fetchEvent) { 137 assert(!fetchEvent->scheduled()); 138 delete fetchEvent; 139 } 140 141 fetchEvent = 142 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 143 fetchEvent->schedule(curTick); 144 } | 129 } 130} 131 132void 133TimingSimpleCPU::resume() 134{ 135 if (_status != SwitchedOut && _status != Idle) { 136 // Delete the old event if it existed. 137 if (fetchEvent) { 138 assert(!fetchEvent->scheduled()); 139 delete fetchEvent; 140 } 141 142 fetchEvent = 143 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 144 fetchEvent->schedule(curTick); 145 } |
145} | |
146 | 146 |
147void 148TimingSimpleCPU::setMemoryMode(State new_mode) 149{ 150 assert(new_mode == SimObject::Timing); | 147 assert(system->getMemoryMode() == System::Timing); 148 changeState(SimObject::Running); |
151} 152 153void 154TimingSimpleCPU::switchOut() 155{ 156 assert(status() == Running || status() == Idle); 157 _status = SwitchedOut; 158 --- 350 unchanged lines hidden (view full) --- 509 advanceInst(fault); 510} 511 512 513void 514TimingSimpleCPU::completeDrain() 515{ 516 DPRINTF(Config, "Done draining\n"); | 149} 150 151void 152TimingSimpleCPU::switchOut() 153{ 154 assert(status() == Running || status() == Idle); 155 _status = SwitchedOut; 156 --- 350 unchanged lines hidden (view full) --- 507 advanceInst(fault); 508} 509 510 511void 512TimingSimpleCPU::completeDrain() 513{ 514 DPRINTF(Config, "Done draining\n"); |
517 changeState(SimObject::DrainedTiming); | 515 changeState(SimObject::Drained); |
518 drainEvent->process(); 519} 520 521bool 522TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 523{ 524 cpu->completeDataAccess(pkt); 525 return true; --- 20 unchanged lines hidden (view full) --- 546// 547BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 548 549 Param<Counter> max_insts_any_thread; 550 Param<Counter> max_insts_all_threads; 551 Param<Counter> max_loads_any_thread; 552 Param<Counter> max_loads_all_threads; 553 SimObjectParam<MemObject *> mem; | 516 drainEvent->process(); 517} 518 519bool 520TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 521{ 522 cpu->completeDataAccess(pkt); 523 return true; --- 20 unchanged lines hidden (view full) --- 544// 545BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 546 547 Param<Counter> max_insts_any_thread; 548 Param<Counter> max_insts_all_threads; 549 Param<Counter> max_loads_any_thread; 550 Param<Counter> max_loads_all_threads; 551 SimObjectParam<MemObject *> mem; |
552 SimObjectParam<System *> system; |
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554 555#if FULL_SYSTEM 556 SimObjectParam<AlphaITB *> itb; 557 SimObjectParam<AlphaDTB *> dtb; | 553 554#if FULL_SYSTEM 555 SimObjectParam<AlphaITB *> itb; 556 SimObjectParam<AlphaDTB *> dtb; |
558 SimObjectParam<System *> system; | |
559 Param<int> cpu_id; 560 Param<Tick> profile; 561#else 562 SimObjectParam<Process *> workload; 563#endif // FULL_SYSTEM 564 565 Param<int> clock; 566 --- 11 unchanged lines hidden (view full) --- 578 "terminate when any thread reaches this inst count"), 579 INIT_PARAM(max_insts_all_threads, 580 "terminate when all threads have reached this inst count"), 581 INIT_PARAM(max_loads_any_thread, 582 "terminate when any thread reaches this load count"), 583 INIT_PARAM(max_loads_all_threads, 584 "terminate when all threads have reached this load count"), 585 INIT_PARAM(mem, "memory"), | 557 Param<int> cpu_id; 558 Param<Tick> profile; 559#else 560 SimObjectParam<Process *> workload; 561#endif // FULL_SYSTEM 562 563 Param<int> clock; 564 --- 11 unchanged lines hidden (view full) --- 576 "terminate when any thread reaches this inst count"), 577 INIT_PARAM(max_insts_all_threads, 578 "terminate when all threads have reached this inst count"), 579 INIT_PARAM(max_loads_any_thread, 580 "terminate when any thread reaches this load count"), 581 INIT_PARAM(max_loads_all_threads, 582 "terminate when all threads have reached this load count"), 583 INIT_PARAM(mem, "memory"), |
584 INIT_PARAM(system, "system object"), |
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586 587#if FULL_SYSTEM 588 INIT_PARAM(itb, "Instruction TLB"), 589 INIT_PARAM(dtb, "Data TLB"), | 585 586#if FULL_SYSTEM 587 INIT_PARAM(itb, "Instruction TLB"), 588 INIT_PARAM(dtb, "Data TLB"), |
590 INIT_PARAM(system, "system object"), | |
591 INIT_PARAM(cpu_id, "processor ID"), 592 INIT_PARAM(profile, ""), 593#else 594 INIT_PARAM(workload, "processes to run"), 595#endif // FULL_SYSTEM 596 597 INIT_PARAM(clock, "clock speed"), 598 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), --- 14 unchanged lines hidden (view full) --- 613 params->max_insts_all_threads = max_insts_all_threads; 614 params->max_loads_any_thread = max_loads_any_thread; 615 params->max_loads_all_threads = max_loads_all_threads; 616 params->deferRegistration = defer_registration; 617 params->clock = clock; 618 params->functionTrace = function_trace; 619 params->functionTraceStart = function_trace_start; 620 params->mem = mem; | 589 INIT_PARAM(cpu_id, "processor ID"), 590 INIT_PARAM(profile, ""), 591#else 592 INIT_PARAM(workload, "processes to run"), 593#endif // FULL_SYSTEM 594 595 INIT_PARAM(clock, "clock speed"), 596 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), --- 14 unchanged lines hidden (view full) --- 611 params->max_insts_all_threads = max_insts_all_threads; 612 params->max_loads_any_thread = max_loads_any_thread; 613 params->max_loads_all_threads = max_loads_all_threads; 614 params->deferRegistration = defer_registration; 615 params->clock = clock; 616 params->functionTrace = function_trace; 617 params->functionTraceStart = function_trace_start; 618 params->mem = mem; |
619 params->system = system; |
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621 622#if FULL_SYSTEM 623 params->itb = itb; 624 params->dtb = dtb; | 620 621#if FULL_SYSTEM 622 params->itb = itb; 623 params->dtb = dtb; |
625 params->system = system; | |
626 params->cpu_id = cpu_id; 627 params->profile = profile; 628#else 629 params->process = workload; 630#endif 631 632 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 633 return cpu; 634} 635 636REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 637 | 624 params->cpu_id = cpu_id; 625 params->profile = profile; 626#else 627 params->process = workload; 628#endif 629 630 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 631 return cpu; 632} 633 634REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 635 |