timing.cc (2866:9b2e1d16d0aa) timing.cc (2867:cc92d58a3210)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
91 drainEvent = NULL;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
91 drainEvent = NULL;
92 fetchEvent = NULL;
92 state = SimObject::Timing;
93}
94
95
96TimingSimpleCPU::~TimingSimpleCPU()
97{
98}
99

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125 return false;
126 }
127}
128
129void
130TimingSimpleCPU::resume()
131{
132 if (_status != SwitchedOut && _status != Idle) {
93 state = SimObject::Timing;
94}
95
96
97TimingSimpleCPU::~TimingSimpleCPU()
98{
99}
100

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126 return false;
127 }
128}
129
130void
131TimingSimpleCPU::resume()
132{
133 if (_status != SwitchedOut && _status != Idle) {
133 Event *e =
134 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
135 e->schedule(curTick);
134 // Delete the old event if it existed.
135 if (fetchEvent) {
136 assert(!fetchEvent->scheduled());
137 delete fetchEvent;
138 }
139
140 fetchEvent =
141 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
142 fetchEvent->schedule(curTick);
136 }
137}
138
139void
140TimingSimpleCPU::setMemoryMode(State new_mode)
141{
142 assert(new_mode == SimObject::Timing);
143}
144
145void
146TimingSimpleCPU::switchOut()
147{
148 assert(status() == Running || status() == Idle);
149 _status = SwitchedOut;
143 }
144}
145
146void
147TimingSimpleCPU::setMemoryMode(State new_mode)
148{
149 assert(new_mode == SimObject::Timing);
150}
151
152void
153TimingSimpleCPU::switchOut()
154{
155 assert(status() == Running || status() == Idle);
156 _status = SwitchedOut;
157
158 // If we've been scheduled to resume but are then told to switch out,
159 // we'll need to cancel it.
160 if (fetchEvent && fetchEvent->scheduled())
161 fetchEvent->deschedule();
150}
151
152
153void
154TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
155{
156 BaseCPU::takeOverFrom(oldCPU);
157

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173 assert(thread_num == 0);
174 assert(thread);
175
176 assert(_status == Idle);
177
178 notIdleFraction++;
179 _status = Running;
180 // kick things off by initiating the fetch of the next instruction
162}
163
164
165void
166TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
167{
168 BaseCPU::takeOverFrom(oldCPU);
169

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185 assert(thread_num == 0);
186 assert(thread);
187
188 assert(_status == Idle);
189
190 notIdleFraction++;
191 _status = Running;
192 // kick things off by initiating the fetch of the next instruction
181 Event *e =
182 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
183 e->schedule(curTick + cycles(delay));
193 fetchEvent =
194 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
195 fetchEvent->schedule(curTick + cycles(delay));
184}
185
186
187void
188TimingSimpleCPU::suspendContext(int thread_num)
189{
190 assert(thread_num == 0);
191 assert(thread);

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197
198
199void
200TimingSimpleCPU::suspendContext(int thread_num)
201{
202 assert(thread_num == 0);
203 assert(thread);

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