timing.cc (2855:5ca2cdb32521) timing.cc (2856:89691405ec9c)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
40Port *
41TimingSimpleCPU::getPort(const std::string &if_name, int idx)
42{
43 if (if_name == "dcache_port")
44 return &dcachePort;
45 else if (if_name == "icache_port")
46 return &icachePort;
47 else
48 panic("No Such Port\n");
49}
40
41void
42TimingSimpleCPU::init()
43{
50
51void
52TimingSimpleCPU::init()
53{
44 //Create Memory Ports (conect them up)
45 Port *mem_dport = mem->getPort("");
46 dcachePort.setPeer(mem_dport);
47 mem_dport->setPeer(&dcachePort);
48
49 Port *mem_iport = mem->getPort("");
50 icachePort.setPeer(mem_iport);
51 mem_iport->setPeer(&icachePort);
52
53 BaseCPU::init();
54#if FULL_SYSTEM
55 for (int i = 0; i < threadContexts.size(); ++i) {
56 ThreadContext *tc = threadContexts[i];
57
58 // initialize CPU, including PC
59 TheISA::initCPU(tc, tc->readCpuId());
60 }

--- 569 unchanged lines hidden --- 		54 BaseCPU::init();
55#if FULL_SYSTEM
56 for (int i = 0; i < threadContexts.size(); ++i) {
57 ThreadContext *tc = threadContexts[i];
58
59 // initialize CPU, including PC
60 TheISA::initCPU(tc, tc->readCpuId());
61 }

--- 569 unchanged lines hidden ---