timing.cc (2839:d5dd8a3cdea0) timing.cc (2855:5ca2cdb32521)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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446 advanceInst(fault);
447 }
448}
449
450
451bool
452TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
453{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 437 unchanged lines hidden (view full) ---

446 advanceInst(fault);
447 }
448}
449
450
451bool
452TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
453{
454 cpu->completeIfetch(pkt);
454 if (cpu->_status == DcacheWaitResponse)
455 cpu->completeDataAccess(pkt);
456 else if (cpu->_status == IcacheWaitResponse)
457 cpu->completeIfetch(pkt);
458 else
459 assert("OOPS" && 0);
455 return true;
456}
457
458void
459TimingSimpleCPU::IcachePort::recvRetry()
460{
461 // we shouldn't get a retry unless we have a packet that we're
462 // waiting to transmit

--- 162 unchanged lines hidden --- 		460 return true;
461}
462
463void
464TimingSimpleCPU::IcachePort::recvRetry()
465{
466 // we shouldn't get a retry unless we have a packet that we're
467 // waiting to transmit

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