timing.cc (2836:c8f549058964) timing.cc (2839:d5dd8a3cdea0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
91 quiesceEvent = NULL;
91 drainEvent = NULL;
92 state = SimObject::Timing;
93}
94
95
96TimingSimpleCPU::~TimingSimpleCPU()
97{
98}
99

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107void
108TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
109{
110 UNSERIALIZE_ENUM(_status);
111 BaseSimpleCPU::unserialize(cp, section);
112}
113
114bool
92 state = SimObject::Timing;
93}
94
95
96TimingSimpleCPU::~TimingSimpleCPU()
97{
98}
99

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107void
108TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
109{
110 UNSERIALIZE_ENUM(_status);
111 BaseSimpleCPU::unserialize(cp, section);
112}
113
114bool
115TimingSimpleCPU::quiesce(Event *quiesce_event)
115TimingSimpleCPU::drain(Event *drain_event)
116{
116{
117 // TimingSimpleCPU is ready to quiesce if it's not waiting for
117 // TimingSimpleCPU is ready to drain if it's not waiting for
118 // an access to complete.
119 if (status() == Idle || status() == Running || status() == SwitchedOut) {
118 // an access to complete.
119 if (status() == Idle || status() == Running || status() == SwitchedOut) {
120 DPRINTF(Config, "Ready to quiesce\n");
121 changeState(SimObject::QuiescedTiming);
120 changeState(SimObject::DrainedTiming);
122 return false;
123 } else {
121 return false;
122 } else {
124 DPRINTF(Config, "Waiting to quiesce\n");
125 changeState(SimObject::Quiescing);
126 quiesceEvent = quiesce_event;
123 changeState(SimObject::Draining);
124 drainEvent = drain_event;
127 return true;
128 }
129}
130
131void
132TimingSimpleCPU::resume()
133{
134 if (_status != SwitchedOut && _status != Idle) {

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418 assert(pkt->result == Packet::Success);
419 assert(_status == IcacheWaitResponse);
420
421 _status = Running;
422
423 delete pkt->req;
424 delete pkt;
425
125 return true;
126 }
127}
128
129void
130TimingSimpleCPU::resume()
131{
132 if (_status != SwitchedOut && _status != Idle) {

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416 assert(pkt->result == Packet::Success);
417 assert(_status == IcacheWaitResponse);
418
419 _status = Running;
420
421 delete pkt->req;
422 delete pkt;
423
426 if (getState() == SimObject::Quiescing) {
427 completeQuiesce();
424 if (getState() == SimObject::Draining) {
425 completeDrain();
428 return;
429 }
430
431 preExecute();
432 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
433 // load or store: just send to dcache
434 Fault fault = curStaticInst->initiateAcc(this, traceData);
435 if (fault == NoFault) {

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475TimingSimpleCPU::completeDataAccess(Packet *pkt)
476{
477 // received a response from the dcache: complete the load or store
478 // instruction
479 assert(pkt->result == Packet::Success);
480 assert(_status == DcacheWaitResponse);
481 _status = Running;
482
426 return;
427 }
428
429 preExecute();
430 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
431 // load or store: just send to dcache
432 Fault fault = curStaticInst->initiateAcc(this, traceData);
433 if (fault == NoFault) {

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473TimingSimpleCPU::completeDataAccess(Packet *pkt)
474{
475 // received a response from the dcache: complete the load or store
476 // instruction
477 assert(pkt->result == Packet::Success);
478 assert(_status == DcacheWaitResponse);
479 _status = Running;
480
483 if (getState() == SimObject::Quiescing) {
484 completeQuiesce();
481 if (getState() == SimObject::Draining) {
482 completeDrain();
485
486 delete pkt->req;
487 delete pkt;
488
489 return;
490 }
491
492 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
493
494 delete pkt->req;
495 delete pkt;
496
497 postExecute();
498 advanceInst(fault);
499}
500
501
502void
483
484 delete pkt->req;
485 delete pkt;
486
487 return;
488 }
489
490 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
491
492 delete pkt->req;
493 delete pkt;
494
495 postExecute();
496 advanceInst(fault);
497}
498
499
500void
503TimingSimpleCPU::completeQuiesce()
501TimingSimpleCPU::completeDrain()
504{
502{
505 DPRINTF(Config, "Done quiescing\n");
506 changeState(SimObject::QuiescedTiming);
507 quiesceEvent->process();
503 DPRINTF(Config, "Done draining\n");
504 changeState(SimObject::DrainedTiming);
505 drainEvent->process();
508}
509
510bool
511TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
512{
513 cpu->completeDataAccess(pkt);
514 return true;
515}

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507
508bool
509TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
510{
511 cpu->completeDataAccess(pkt);
512 return true;
513}

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