timing.cc (2823:ff50d1693ee5) timing.cc (2835:d2a977df88de)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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113
114bool
115TimingSimpleCPU::quiesce(Event *quiesce_event)
116{
117 // TimingSimpleCPU is ready to quiesce if it's not waiting for
118 // an access to complete.
119 if (status() == Idle || status() == Running || status() == SwitchedOut) {
120 DPRINTF(Config, "Ready to quiesce\n");
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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113
114bool
115TimingSimpleCPU::quiesce(Event *quiesce_event)
116{
117 // TimingSimpleCPU is ready to quiesce if it's not waiting for
118 // an access to complete.
119 if (status() == Idle || status() == Running || status() == SwitchedOut) {
120 DPRINTF(Config, "Ready to quiesce\n");
121 changeState(SimObject::QuiescedTiming);
122 return false;
123 } else {
124 DPRINTF(Config, "Waiting to quiesce\n");
125 changeState(SimObject::Quiescing);
126 quiesceEvent = quiesce_event;
127 return true;
128 }
129}

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203
204
205template <class T>
206Fault
207TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
208{
209 // need to fill in CPU & thread IDs here
210 Request *data_read_req = new Request();
121 return false;
122 } else {
123 DPRINTF(Config, "Waiting to quiesce\n");
124 changeState(SimObject::Quiescing);
125 quiesceEvent = quiesce_event;
126 return true;
127 }
128}

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202
203
204template <class T>
205Fault
206TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
207{
208 // need to fill in CPU & thread IDs here
209 Request *data_read_req = new Request();
211
210 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
212 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
213
214 if (traceData) {
215 traceData->setAddr(data_read_req->getVaddr());
216 }
217
218 // translate to physical address
219 Fault fault = thread->translateDataReadReq(data_read_req);

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284
285
286template <class T>
287Fault
288TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
289{
290 // need to fill in CPU & thread IDs here
291 Request *data_write_req = new Request();
211 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
212
213 if (traceData) {
214 traceData->setAddr(data_read_req->getVaddr());
215 }
216
217 // translate to physical address
218 Fault fault = thread->translateDataReadReq(data_read_req);

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283
284
285template <class T>
286Fault
287TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
288{
289 // need to fill in CPU & thread IDs here
290 Request *data_write_req = new Request();
291 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
292 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
293
294 // translate to physical address
295 Fault fault = thread->translateDataWriteReq(data_write_req);
296 // Now do the access.
297 if (fault == NoFault) {
298 Packet *data_write_pkt =
299 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);

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367
368void
369TimingSimpleCPU::fetch()
370{
371 checkForInterrupts();
372
373 // need to fill in CPU & thread IDs here
374 Request *ifetch_req = new Request();
292 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
293
294 // translate to physical address
295 Fault fault = thread->translateDataWriteReq(data_write_req);
296 // Now do the access.
297 if (fault == NoFault) {
298 Packet *data_write_pkt =
299 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);

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367
368void
369TimingSimpleCPU::fetch()
370{
371 checkForInterrupts();
372
373 // need to fill in CPU & thread IDs here
374 Request *ifetch_req = new Request();
375 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
375 Fault fault = setupFetchRequest(ifetch_req);
376
377 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
378 ifetch_pkt->dataStatic(&inst);
379
380 if (fault == NoFault) {
381 if (!icachePort.sendTiming(ifetch_pkt)) {
382 // Need to wait for retry

--- 242 unchanged lines hidden --- 		376 Fault fault = setupFetchRequest(ifetch_req);
377
378 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
379 ifetch_pkt->dataStatic(&inst);
380
381 if (fault == NoFault) {
382 if (!icachePort.sendTiming(ifetch_pkt)) {
383 // Need to wait for retry

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