timing.cc (2680:246e7104f744) timing.cc (2683:d6b72bb2ed97)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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136 }
137}
138
139
140void
141TimingSimpleCPU::activateContext(int thread_num, int delay)
142{
143 assert(thread_num == 0);
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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136 }
137}
138
139
140void
141TimingSimpleCPU::activateContext(int thread_num, int delay)
142{
143 assert(thread_num == 0);
144 assert(cpuXC);
144 assert(thread);
145
146 assert(_status == Idle);
147
148 notIdleFraction++;
149 _status = Running;
150 // kick things off by initiating the fetch of the next instruction
151 Event *e =
152 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
153 e->schedule(curTick + cycles(delay));
154}
155
156
157void
158TimingSimpleCPU::suspendContext(int thread_num)
159{
160 assert(thread_num == 0);
145
146 assert(_status == Idle);
147
148 notIdleFraction++;
149 _status = Running;
150 // kick things off by initiating the fetch of the next instruction
151 Event *e =
152 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
153 e->schedule(curTick + cycles(delay));
154}
155
156
157void
158TimingSimpleCPU::suspendContext(int thread_num)
159{
160 assert(thread_num == 0);
161 assert(cpuXC);
161 assert(thread);
162
163 assert(_status == Running);
164
165 // just change status to Idle... if status != Running,
166 // completeInst() will not initiate fetch of next instruction.
167
168 notIdleFraction--;
169 _status = Idle;
170}
171
172
173template <class T>
174Fault
175TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
176{
177 // need to fill in CPU & thread IDs here
178 Request *data_read_req = new Request();
179
162
163 assert(_status == Running);
164
165 // just change status to Idle... if status != Running,
166 // completeInst() will not initiate fetch of next instruction.
167
168 notIdleFraction--;
169 _status = Idle;
170}
171
172
173template <class T>
174Fault
175TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
176{
177 // need to fill in CPU & thread IDs here
178 Request *data_read_req = new Request();
179
180 data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
180 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
181
182 if (traceData) {
183 traceData->setAddr(data_read_req->getVaddr());
184 }
185
186 // translate to physical address
181
182 if (traceData) {
183 traceData->setAddr(data_read_req->getVaddr());
184 }
185
186 // translate to physical address
187 Fault fault = cpuXC->translateDataReadReq(data_read_req);
187 Fault fault = thread->translateDataReadReq(data_read_req);
188
189 // Now do the access.
190 if (fault == NoFault) {
191 Packet *data_read_pkt =
192 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
193 data_read_pkt->dataDynamic<T>(new T);
194
195 if (!dcachePort.sendTiming(data_read_pkt)) {

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252
253
254template <class T>
255Fault
256TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
257{
258 // need to fill in CPU & thread IDs here
259 Request *data_write_req = new Request();
188
189 // Now do the access.
190 if (fault == NoFault) {
191 Packet *data_read_pkt =
192 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
193 data_read_pkt->dataDynamic<T>(new T);
194
195 if (!dcachePort.sendTiming(data_read_pkt)) {

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252
253
254template <class T>
255Fault
256TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
257{
258 // need to fill in CPU & thread IDs here
259 Request *data_write_req = new Request();
260 data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
260 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
261
262 // translate to physical address
261
262 // translate to physical address
263 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
263 Fault fault = thread->translateDataWriteReq(data_write_req);
264 // Now do the access.
265 if (fault == NoFault) {
266 Packet *data_write_pkt =
267 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
268 data_write_pkt->allocate();
269 data_write_pkt->set(data);
270
271 if (!dcachePort.sendTiming(data_write_pkt)) {

--- 299 unchanged lines hidden --- 		264 // Now do the access.
265 if (fault == NoFault) {
266 Packet *data_write_pkt =
267 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
268 data_write_pkt->allocate();
269 data_write_pkt->set(data);
270
271 if (!dcachePort.sendTiming(data_write_pkt)) {

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