timing.cc (2665:a124942bacb8) timing.cc (2680:246e7104f744)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47 mem_dport->setPeer(&dcachePort);
48
49 Port *mem_iport = mem->getPort("");
50 icachePort.setPeer(mem_iport);
51 mem_iport->setPeer(&icachePort);
52
53 BaseCPU::init();
54#if FULL_SYSTEM
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 38 unchanged lines hidden (view full) ---

47 mem_dport->setPeer(&dcachePort);
48
49 Port *mem_iport = mem->getPort("");
50 icachePort.setPeer(mem_iport);
51 mem_iport->setPeer(&icachePort);
52
53 BaseCPU::init();
54#if FULL_SYSTEM
55 for (int i = 0; i < execContexts.size(); ++i) {
56 ExecContext *xc = execContexts[i];
55 for (int i = 0; i < threadContexts.size(); ++i) {
56 ThreadContext *tc = threadContexts[i];
57
58 // initialize CPU, including PC
57
58 // initialize CPU, including PC
59 TheISA::initCPU(xc, xc->readCpuId());
59 TheISA::initCPU(tc, tc->readCpuId());
60 }
61#endif
62}
63
64Tick
65TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
66{
67 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");

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120}
121
122
123void
124TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
125{
126 BaseCPU::takeOverFrom(oldCPU);
127
60 }
61#endif
62}
63
64Tick
65TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
66{
67 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");

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120}
121
122
123void
124TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
125{
126 BaseCPU::takeOverFrom(oldCPU);
127
128 // if any of this CPU's ExecContexts are active, mark the CPU as
128 // if any of this CPU's ThreadContexts are active, mark the CPU as
129 // running and schedule its tick event.
129 // running and schedule its tick event.
130 for (int i = 0; i < execContexts.size(); ++i) {
131 ExecContext *xc = execContexts[i];
132 if (xc->status() == ExecContext::Active && _status != Running) {
130 for (int i = 0; i < threadContexts.size(); ++i) {
131 ThreadContext *tc = threadContexts[i];
132 if (tc->status() == ThreadContext::Active && _status != Running) {
133 _status = Running;
134 break;
135 }
136 }
137}
138
139
140void

--- 430 unchanged lines hidden --- 		133 _status = Running;
134 break;
135 }
136 }
137}
138
139
140void

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