timing.cc (2644:8a45565c2c04) | timing.cc (2657:b119b774656b) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 405 unchanged lines hidden (view full) --- 414 415bool 416TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 417{ 418 cpu->completeIfetch(pkt); 419 return true; 420} 421 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 405 unchanged lines hidden (view full) --- 414 415bool 416TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 417{ 418 cpu->completeIfetch(pkt); 419 return true; 420} 421 |
422Packet * | 422void |
423TimingSimpleCPU::IcachePort::recvRetry() 424{ 425 // we shouldn't get a retry unless we have a packet that we're 426 // waiting to transmit 427 assert(cpu->ifetch_pkt != NULL); 428 assert(cpu->_status == IcacheRetry); | 423TimingSimpleCPU::IcachePort::recvRetry() 424{ 425 // we shouldn't get a retry unless we have a packet that we're 426 // waiting to transmit 427 assert(cpu->ifetch_pkt != NULL); 428 assert(cpu->_status == IcacheRetry); |
429 cpu->_status = IcacheWaitResponse; | |
430 Packet *tmp = cpu->ifetch_pkt; | 429 Packet *tmp = cpu->ifetch_pkt; |
431 cpu->ifetch_pkt = NULL; 432 return tmp; | 430 if (sendTiming(tmp)) { 431 cpu->_status = IcacheWaitResponse; 432 cpu->ifetch_pkt = NULL; 433 } |
433} 434 435void 436TimingSimpleCPU::completeDataAccess(Packet *pkt) 437{ 438 // received a response from the dcache: complete the load or store 439 // instruction 440 assert(pkt->result == Packet::Success); --- 13 unchanged lines hidden (view full) --- 454 455bool 456TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 457{ 458 cpu->completeDataAccess(pkt); 459 return true; 460} 461 | 434} 435 436void 437TimingSimpleCPU::completeDataAccess(Packet *pkt) 438{ 439 // received a response from the dcache: complete the load or store 440 // instruction 441 assert(pkt->result == Packet::Success); --- 13 unchanged lines hidden (view full) --- 455 456bool 457TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 458{ 459 cpu->completeDataAccess(pkt); 460 return true; 461} 462 |
462Packet * | 463void |
463TimingSimpleCPU::DcachePort::recvRetry() 464{ 465 // we shouldn't get a retry unless we have a packet that we're 466 // waiting to transmit 467 assert(cpu->dcache_pkt != NULL); 468 assert(cpu->_status == DcacheRetry); | 464TimingSimpleCPU::DcachePort::recvRetry() 465{ 466 // we shouldn't get a retry unless we have a packet that we're 467 // waiting to transmit 468 assert(cpu->dcache_pkt != NULL); 469 assert(cpu->_status == DcacheRetry); |
469 cpu->_status = DcacheWaitResponse; | |
470 Packet *tmp = cpu->dcache_pkt; | 470 Packet *tmp = cpu->dcache_pkt; |
471 cpu->dcache_pkt = NULL; 472 return tmp; | 471 if (sendTiming(tmp)) { 472 cpu->_status = DcacheWaitResponse; 473 cpu->dcache_pkt = NULL; 474 } |
473} 474 475 476//////////////////////////////////////////////////////////////////////// 477// 478// TimingSimpleCPU Simulation Object 479// 480BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) --- 90 unchanged lines hidden --- | 475} 476 477 478//////////////////////////////////////////////////////////////////////// 479// 480// TimingSimpleCPU Simulation Object 481// 482BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) --- 90 unchanged lines hidden --- |