timing.cc (2641:6d9d837e2032) timing.cc (2644:8a45565c2c04)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154
155void
156TimingSimpleCPU::suspendContext(int thread_num)
157{
158 assert(thread_num == 0);
159 assert(cpuXC);
160
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154
155void
156TimingSimpleCPU::suspendContext(int thread_num)
157{
158 assert(thread_num == 0);
159 assert(cpuXC);
160
161 panic("TimingSimpleCPU::suspendContext not implemented");
162
163 assert(_status == Running);
164
161 assert(_status == Running);
162
163 // just change status to Idle... if status != Running,
164 // completeInst() will not initiate fetch of next instruction.
165
165 notIdleFraction--;
166 _status = Idle;
167}
168
169
170template <class T>
171Fault
172TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)

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352 _status = IcacheRetry;
353 } else {
354 // Need to wait for cache to respond
355 _status = IcacheWaitResponse;
356 // ownership of packet transferred to memory system
357 ifetch_pkt = NULL;
358 }
359 } else {
166 notIdleFraction--;
167 _status = Idle;
168}
169
170
171template <class T>
172Fault
173TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)

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353 _status = IcacheRetry;
354 } else {
355 // Need to wait for cache to respond
356 _status = IcacheWaitResponse;
357 // ownership of packet transferred to memory system
358 ifetch_pkt = NULL;
359 }
360 } else {
360 panic("TimingSimpleCPU fetch fault handling not implemented");
361 // fetch fault: advance directly to next instruction (fault handler)
362 advanceInst(fault);
361 }
362}
363
364
365void
363 }
364}
365
366
367void
366TimingSimpleCPU::completeInst(Fault fault)
368TimingSimpleCPU::advanceInst(Fault fault)
367{
369{
368 postExecute();
369
370 if (traceData) {
371 traceData->finalize();
372 }
373
374 advancePC(fault);
375
376 if (_status == Running) {
377 // kick off fetch of next instruction... callback from icache
378 // response will cause that instruction to be executed,
379 // keeping the CPU running.
380 fetch();
381 }
382}
383
384
385void
370 advancePC(fault);
371
372 if (_status == Running) {
373 // kick off fetch of next instruction... callback from icache
374 // response will cause that instruction to be executed,
375 // keeping the CPU running.
376 fetch();
377 }
378}
379
380
381void
386TimingSimpleCPU::completeIfetch()
382TimingSimpleCPU::completeIfetch(Packet *pkt)
387{
388 // received a response from the icache: execute the received
389 // instruction
383{
384 // received a response from the icache: execute the received
385 // instruction
386 assert(pkt->result == Packet::Success);
390 assert(_status == IcacheWaitResponse);
391 _status = Running;
387 assert(_status == IcacheWaitResponse);
388 _status = Running;
389
390 delete pkt->req;
391 delete pkt;
392
392 preExecute();
393 preExecute();
393 if (curStaticInst->isMemRef()) {
394 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
394 // load or store: just send to dcache
395 Fault fault = curStaticInst->initiateAcc(this, traceData);
395 // load or store: just send to dcache
396 Fault fault = curStaticInst->initiateAcc(this, traceData);
396 assert(fault == NoFault);
397 assert(_status == DcacheWaitResponse);
398 // instruction will complete in dcache response callback
397 if (fault == NoFault) {
398 // successfully initiated access: instruction will
399 // complete in dcache response callback
400 assert(_status == DcacheWaitResponse);
401 } else {
402 // fault: complete now to invoke fault handler
403 postExecute();
404 advanceInst(fault);
405 }
399 } else {
400 // non-memory instruction: execute completely now
401 Fault fault = curStaticInst->execute(this, traceData);
406 } else {
407 // non-memory instruction: execute completely now
408 Fault fault = curStaticInst->execute(this, traceData);
402 completeInst(fault);
409 postExecute();
410 advanceInst(fault);
403 }
404}
405
406
407bool
408TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
409{
411 }
412}
413
414
415bool
416TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
417{
410 cpu->completeIfetch();
418 cpu->completeIfetch(pkt);
411 return true;
412}
413
414Packet *
415TimingSimpleCPU::IcachePort::recvRetry()
416{
417 // we shouldn't get a retry unless we have a packet that we're
418 // waiting to transmit

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430 // received a response from the dcache: complete the load or store
431 // instruction
432 assert(pkt->result == Packet::Success);
433 assert(_status == DcacheWaitResponse);
434 _status = Running;
435
436 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
437
419 return true;
420}
421
422Packet *
423TimingSimpleCPU::IcachePort::recvRetry()
424{
425 // we shouldn't get a retry unless we have a packet that we're
426 // waiting to transmit

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438 // received a response from the dcache: complete the load or store
439 // instruction
440 assert(pkt->result == Packet::Success);
441 assert(_status == DcacheWaitResponse);
442 _status = Running;
443
444 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
445
438 completeInst(fault);
446 delete pkt->req;
447 delete pkt;
448
449 postExecute();
450 advanceInst(fault);
439}
440
441
442
443bool
444TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
445{
446 cpu->completeDataAccess(pkt);

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452
453
454
455bool
456TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
457{
458 cpu->completeDataAccess(pkt);

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