timing.cc (12748:ae5ce8e42de7) timing.cc (12749:223c83ed9979)
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013,2015,2017 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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256}
257
258bool
259TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
260{
261 SimpleExecContext &t_info = *threadInfo[curThread];
262 SimpleThread* thread = t_info.thread;
263
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013,2015,2017 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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256}
257
258bool
259TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
260{
261 SimpleExecContext &t_info = *threadInfo[curThread];
262 SimpleThread* thread = t_info.thread;
263
264 RequestPtr req = pkt->req;
264 const RequestPtr &req = pkt->req;
265
266 // We're about the issues a locked load, so tell the monitor
267 // to start caring about this address
268 if (pkt->isRead() && pkt->req->isLLSC()) {
269 TheISA::handleLockedRead(thread, pkt->req);
270 }
271 if (req->isMmappedIpr()) {
272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);

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280 _status = DcacheWaitResponse;
281 // memory system takes ownership of packet
282 dcache_pkt = NULL;
283 }
284 return dcache_pkt == NULL;
285}
286
287void
265
266 // We're about the issues a locked load, so tell the monitor
267 // to start caring about this address
268 if (pkt->isRead() && pkt->req->isLLSC()) {
269 TheISA::handleLockedRead(thread, pkt->req);
270 }
271 if (req->isMmappedIpr()) {
272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);

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280 _status = DcacheWaitResponse;
281 // memory system takes ownership of packet
282 dcache_pkt = NULL;
283 }
284 return dcache_pkt == NULL;
285}
286
287void
288TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
288TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
289 bool read)
290{
291 SimpleExecContext &t_info = *threadInfo[curThread];
292 SimpleThread* thread = t_info.thread;
293
294 PacketPtr pkt = buildPacket(req, read);
295 pkt->dataDynamic<uint8_t>(data);
296 if (req->getFlags().isSet(Request::NO_ACCESS)) {

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316 } else {
317 _status = DcacheWaitResponse;
318 completeDataAccess(pkt);
319 }
320 }
321}
322
323void
289 bool read)
290{
291 SimpleExecContext &t_info = *threadInfo[curThread];
292 SimpleThread* thread = t_info.thread;
293
294 PacketPtr pkt = buildPacket(req, read);
295 pkt->dataDynamic<uint8_t>(data);
296 if (req->getFlags().isSet(Request::NO_ACCESS)) {

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316 } else {
317 _status = DcacheWaitResponse;
318 completeDataAccess(pkt);
319 }
320 }
321}
322
323void
324TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
325 RequestPtr req, uint8_t *data, bool read)
324TimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
325 const RequestPtr &req, uint8_t *data, bool read)
326{
327 PacketPtr pkt1, pkt2;
328 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
329 if (req->getFlags().isSet(Request::NO_ACCESS)) {
330 assert(!dcache_pkt);
331 pkt1->makeResponse();
332 completeDataAccess(pkt1);
333 } else if (read) {

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372 }
373
374 postExecute();
375
376 advanceInst(fault);
377}
378
379PacketPtr
326{
327 PacketPtr pkt1, pkt2;
328 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
329 if (req->getFlags().isSet(Request::NO_ACCESS)) {
330 assert(!dcache_pkt);
331 pkt1->makeResponse();
332 completeDataAccess(pkt1);
333 } else if (read) {

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372 }
373
374 postExecute();
375
376 advanceInst(fault);
377}
378
379PacketPtr
380TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
380TimingSimpleCPU::buildPacket(const RequestPtr &req, bool read)
381{
382 return read ? Packet::createRead(req) : Packet::createWrite(req);
383}
384
385void
386TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
381{
382 return read ? Packet::createRead(req) : Packet::createWrite(req);
383}
384
385void
386TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
387 RequestPtr req1, RequestPtr req2, RequestPtr req,
387 const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req,
388 uint8_t *data, bool read)
389{
390 pkt1 = pkt2 = NULL;
391
392 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
393
394 if (req->getFlags().isSet(Request::NO_ACCESS)) {
395 pkt1 = buildPacket(req, read);

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433 const int asid = 0;
434 const Addr pc = thread->instAddr();
435 unsigned block_size = cacheLineSize();
436 BaseTLB::Mode mode = BaseTLB::Read;
437
438 if (traceData)
439 traceData->setMem(addr, size, flags);
440
388 uint8_t *data, bool read)
389{
390 pkt1 = pkt2 = NULL;
391
392 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
393
394 if (req->getFlags().isSet(Request::NO_ACCESS)) {
395 pkt1 = buildPacket(req, read);

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433 const int asid = 0;
434 const Addr pc = thread->instAddr();
435 unsigned block_size = cacheLineSize();
436 BaseTLB::Mode mode = BaseTLB::Read;
437
438 if (traceData)
439 traceData->setMem(addr, size, flags);
440
441 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
442 thread->contextId());
441 RequestPtr req = std::make_shared<Request>(
442 asid, addr, size, flags, dataMasterId(), pc,
443 thread->contextId());
443
444 req->taskId(taskId());
445
446 Addr split_addr = roundDown(addr + size - 1, block_size);
447 assert(split_addr <= addr || split_addr - addr < block_size);
448
449 _status = DTBWaitResponse;
450 if (split_addr > addr) {

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474}
475
476bool
477TimingSimpleCPU::handleWritePacket()
478{
479 SimpleExecContext &t_info = *threadInfo[curThread];
480 SimpleThread* thread = t_info.thread;
481
444
445 req->taskId(taskId());
446
447 Addr split_addr = roundDown(addr + size - 1, block_size);
448 assert(split_addr <= addr || split_addr - addr < block_size);
449
450 _status = DTBWaitResponse;
451 if (split_addr > addr) {

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475}
476
477bool
478TimingSimpleCPU::handleWritePacket()
479{
480 SimpleExecContext &t_info = *threadInfo[curThread];
481 SimpleThread* thread = t_info.thread;
482
482 RequestPtr req = dcache_pkt->req;
483 const RequestPtr &req = dcache_pkt->req;
483 if (req->isMmappedIpr()) {
484 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
485 new IprEvent(dcache_pkt, this, clockEdge(delay));
486 _status = DcacheWaitResponse;
487 dcache_pkt = NULL;
488 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
489 _status = DcacheRetry;
490 } else {

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514 memset(newData, 0, size);
515 } else {
516 memcpy(newData, data, size);
517 }
518
519 if (traceData)
520 traceData->setMem(addr, size, flags);
521
484 if (req->isMmappedIpr()) {
485 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
486 new IprEvent(dcache_pkt, this, clockEdge(delay));
487 _status = DcacheWaitResponse;
488 dcache_pkt = NULL;
489 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
490 _status = DcacheRetry;
491 } else {

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515 memset(newData, 0, size);
516 } else {
517 memcpy(newData, data, size);
518 }
519
520 if (traceData)
521 traceData->setMem(addr, size, flags);
522
522 RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
523 thread->contextId());
523 RequestPtr req = std::make_shared<Request>(
524 asid, addr, size, flags, dataMasterId(), pc,
525 thread->contextId());
524
525 req->taskId(taskId());
526
527 Addr split_addr = roundDown(addr + size - 1, block_size);
528 assert(split_addr <= addr || split_addr - addr < block_size);
529
530 _status = DTBWaitResponse;
531 if (split_addr > addr) {

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615 return;
616
617 TheISA::PCState pcState = thread->pcState();
618 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
619 !curMacroStaticInst;
620
621 if (needToFetch) {
622 _status = BaseSimpleCPU::Running;
526
527 req->taskId(taskId());
528
529 Addr split_addr = roundDown(addr + size - 1, block_size);
530 assert(split_addr <= addr || split_addr - addr < block_size);
531
532 _status = DTBWaitResponse;
533 if (split_addr > addr) {

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617 return;
618
619 TheISA::PCState pcState = thread->pcState();
620 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
621 !curMacroStaticInst;
622
623 if (needToFetch) {
624 _status = BaseSimpleCPU::Running;
623 RequestPtr ifetch_req = new Request();
625 RequestPtr ifetch_req = std::make_shared<Request>();
624 ifetch_req->taskId(taskId());
625 ifetch_req->setContext(thread->contextId());
626 setupFetchRequest(ifetch_req);
627 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
628 thread->itb->translateTiming(ifetch_req, thread->getTC(),
629 &fetchTranslation, BaseTLB::Execute);
630 } else {
631 _status = IcacheWaitResponse;
632 completeIfetch(NULL);
633
634 updateCycleCounts();
635 updateCycleCounters(BaseCPU::CPU_STATE_ON);
636 }
637}
638
639
640void
626 ifetch_req->taskId(taskId());
627 ifetch_req->setContext(thread->contextId());
628 setupFetchRequest(ifetch_req);
629 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
630 thread->itb->translateTiming(ifetch_req, thread->getTC(),
631 &fetchTranslation, BaseTLB::Execute);
632 } else {
633 _status = IcacheWaitResponse;
634 completeIfetch(NULL);
635
636 updateCycleCounts();
637 updateCycleCounters(BaseCPU::CPU_STATE_ON);
638 }
639}
640
641
642void
641TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
643TimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req,
642 ThreadContext *tc)
643{
644 if (fault == NoFault) {
645 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
646 req->getVaddr(), req->getPaddr());
647 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
648 ifetch_pkt->dataStatic(&inst);
649 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());

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654 } else {
655 // Need to wait for cache to respond
656 _status = IcacheWaitResponse;
657 // ownership of packet transferred to memory system
658 ifetch_pkt = NULL;
659 }
660 } else {
661 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
644 ThreadContext *tc)
645{
646 if (fault == NoFault) {
647 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
648 req->getVaddr(), req->getPaddr());
649 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
650 ifetch_pkt->dataStatic(&inst);
651 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());

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656 } else {
657 // Need to wait for cache to respond
658 _status = IcacheWaitResponse;
659 // ownership of packet transferred to memory system
660 ifetch_pkt = NULL;
661 }
662 } else {
663 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
662 delete req;
663 // fetch fault: advance directly to next instruction (fault handler)
664 _status = BaseSimpleCPU::Running;
665 advanceInst(fault);
666 }
667
668 updateCycleCounts();
669 updateCycleCounters(BaseCPU::CPU_STATE_ON);
670}

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770 curStaticInst->isFirstMicroop()))
771 instCnt++;
772 advanceInst(fault);
773 } else {
774 advanceInst(NoFault);
775 }
776
777 if (pkt) {
664 // fetch fault: advance directly to next instruction (fault handler)
665 _status = BaseSimpleCPU::Running;
666 advanceInst(fault);
667 }
668
669 updateCycleCounts();
670 updateCycleCounters(BaseCPU::CPU_STATE_ON);
671}

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771 curStaticInst->isFirstMicroop()))
772 instCnt++;
773 advanceInst(fault);
774 } else {
775 advanceInst(NoFault);
776 }
777
778 if (pkt) {
778 delete pkt->req;
779 delete pkt;
780 }
781}
782
783void
784TimingSimpleCPU::IcachePort::ITickEvent::process()
785{
786 cpu->completeIfetch(pkt);

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826
827 updateCycleCounts();
828 updateCycleCounters(BaseCPU::CPU_STATE_ON);
829
830 if (pkt->senderState) {
831 SplitFragmentSenderState * send_state =
832 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
833 assert(send_state);
779 delete pkt;
780 }
781}
782
783void
784TimingSimpleCPU::IcachePort::ITickEvent::process()
785{
786 cpu->completeIfetch(pkt);

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826
827 updateCycleCounts();
828 updateCycleCounters(BaseCPU::CPU_STATE_ON);
829
830 if (pkt->senderState) {
831 SplitFragmentSenderState * send_state =
832 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
833 assert(send_state);
834 delete pkt->req;
835 delete pkt;
836 PacketPtr big_pkt = send_state->bigPkt;
837 delete send_state;
838
839 SplitMainSenderState * main_send_state =
840 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
841 assert(main_send_state);
842 // Record the fact that this packet is no longer outstanding.

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861 if (fault == NoFault)
862 countInst();
863 else if (traceData) {
864 // If there was a fault, we shouldn't trace this instruction.
865 delete traceData;
866 traceData = NULL;
867 }
868
834 delete pkt;
835 PacketPtr big_pkt = send_state->bigPkt;
836 delete send_state;
837
838 SplitMainSenderState * main_send_state =
839 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
840 assert(main_send_state);
841 // Record the fact that this packet is no longer outstanding.

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860 if (fault == NoFault)
861 countInst();
862 else if (traceData) {
863 // If there was a fault, we shouldn't trace this instruction.
864 delete traceData;
865 traceData = NULL;
866 }
867
869 delete pkt->req;
870 delete pkt;
871
872 postExecute();
873
874 advanceInst(fault);
875}
876
877void

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869
870 postExecute();
871
872 advanceInst(fault);
873}
874
875void

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