timing.cc (10665:aef704eaedd2) timing.cc (10669:aae98c1cf4a0)
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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713TimingSimpleCPU::IcachePort::ITickEvent::process()
714{
715 cpu->completeIfetch(pkt);
716}
717
718bool
719TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
720{
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 704 unchanged lines hidden (view full) ---

713TimingSimpleCPU::IcachePort::ITickEvent::process()
714{
715 cpu->completeIfetch(pkt);
716}
717
718bool
719TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
720{
721 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
721 DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
722 // we should only ever see one response per cycle since we only
723 // issue a new request once this response is sunk
724 assert(!tickEvent.scheduled());
722 // delay processing of returned data until next CPU clock edge
725 // delay processing of returned data until next CPU clock edge
723 Tick next_tick = cpu->clockEdge();
726 tickEvent.schedule(pkt, cpu->clockEdge());
724
727
725 if (next_tick == curTick())
726 cpu->completeIfetch(pkt);
727 else
728 tickEvent.schedule(pkt, next_tick);
729
730 return true;
731}
732
733void
734TimingSimpleCPU::IcachePort::recvRetry()
735{
736 // we shouldn't get a retry unless we have a packet that we're
737 // waiting to transmit

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831 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
832 cpu->wakeup();
833 }
834}
835
836bool
837TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
838{
728 return true;
729}
730
731void
732TimingSimpleCPU::IcachePort::recvRetry()
733{
734 // we shouldn't get a retry unless we have a packet that we're
735 // waiting to transmit

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829 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
830 cpu->wakeup();
831 }
832}
833
834bool
835TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
836{
839 // delay processing of returned data until next CPU clock edge
840 Tick next_tick = cpu->clockEdge();
837 DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
841
838
842 if (next_tick == curTick()) {
843 cpu->completeDataAccess(pkt);
839 // The timing CPU is not really ticked, instead it relies on the
840 // memory system (fetch and load/store) to set the pace.
841 if (!tickEvent.scheduled()) {
842 // Delay processing of returned data until next CPU clock edge
843 tickEvent.schedule(pkt, cpu->clockEdge());
844 return true;
844 } else {
845 } else {
845 if (!tickEvent.scheduled()) {
846 tickEvent.schedule(pkt, next_tick);
847 } else {
848 // In the case of a split transaction and a cache that is
849 // faster than a CPU we could get two responses before
850 // next_tick expires
851 if (!retryEvent.scheduled())
852 cpu->schedule(retryEvent, next_tick);
853 return false;
854 }
846 // In the case of a split transaction and a cache that is
847 // faster than a CPU we could get two responses in the
848 // same tick, delay the second one
849 if (!retryEvent.scheduled())
850 cpu->schedule(retryEvent, cpu->clockEdge(Cycles(1)));
851 return false;
855 }
852 }
856
857 return true;
858}
859
860void
861TimingSimpleCPU::DcachePort::DTickEvent::process()
862{
863 cpu->completeDataAccess(pkt);
864}
865

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854
855void
856TimingSimpleCPU::DcachePort::DTickEvent::process()
857{
858 cpu->completeDataAccess(pkt);
859}
860

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