timing.cc (10596:1eec33d2fc52) | timing.cc (10653:e3fc6bc7f97e) |
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1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 256 unchanged lines hidden (view full) --- 265 } 266 return dcache_pkt == NULL; 267} 268 269void 270TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 271 bool read) 272{ | 1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2010-2013 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 256 unchanged lines hidden (view full) --- 265 } 266 return dcache_pkt == NULL; 267} 268 269void 270TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 271 bool read) 272{ |
273 PacketPtr pkt; 274 buildPacket(pkt, req, read); | 273 PacketPtr pkt = buildPacket(req, read); |
275 pkt->dataDynamic<uint8_t>(data); 276 if (req->getFlags().isSet(Request::NO_ACCESS)) { 277 assert(!dcache_pkt); 278 pkt->makeResponse(); 279 completeDataAccess(pkt); 280 } else if (read) { 281 handleReadPacket(pkt); 282 } else { --- 66 unchanged lines hidden (view full) --- 349 traceData = NULL; 350 } 351 352 postExecute(); 353 354 advanceInst(fault); 355} 356 | 274 pkt->dataDynamic<uint8_t>(data); 275 if (req->getFlags().isSet(Request::NO_ACCESS)) { 276 assert(!dcache_pkt); 277 pkt->makeResponse(); 278 completeDataAccess(pkt); 279 } else if (read) { 280 handleReadPacket(pkt); 281 } else { --- 66 unchanged lines hidden (view full) --- 348 traceData = NULL; 349 } 350 351 postExecute(); 352 353 advanceInst(fault); 354} 355 |
357void 358TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) | 356PacketPtr 357TimingSimpleCPU::buildPacket(RequestPtr req, bool read) |
359{ | 358{ |
360 pkt = read ? Packet::createRead(req) : Packet::createWrite(req); | 359 return read ? Packet::createRead(req) : Packet::createWrite(req); |
361} 362 363void 364TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 365 RequestPtr req1, RequestPtr req2, RequestPtr req, 366 uint8_t *data, bool read) 367{ 368 pkt1 = pkt2 = NULL; 369 370 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 371 372 if (req->getFlags().isSet(Request::NO_ACCESS)) { | 360} 361 362void 363TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 364 RequestPtr req1, RequestPtr req2, RequestPtr req, 365 uint8_t *data, bool read) 366{ 367 pkt1 = pkt2 = NULL; 368 369 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); 370 371 if (req->getFlags().isSet(Request::NO_ACCESS)) { |
373 buildPacket(pkt1, req, read); | 372 pkt1 = buildPacket(req, read); |
374 return; 375 } 376 | 373 return; 374 } 375 |
377 buildPacket(pkt1, req1, read); 378 buildPacket(pkt2, req2, read); | 376 pkt1 = buildPacket(req1, read); 377 pkt2 = buildPacket(req2, read); |
379 | 378 |
380 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); | |
381 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 382 383 pkt->dataDynamic<uint8_t>(data); 384 pkt1->dataStatic<uint8_t>(data); 385 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 386 387 SplitMainSenderState * main_send_state = new SplitMainSenderState; 388 pkt->senderState = main_send_state; --- 564 unchanged lines hidden --- | 379 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 380 381 pkt->dataDynamic<uint8_t>(data); 382 pkt1->dataStatic<uint8_t>(data); 383 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 384 385 SplitMainSenderState * main_send_state = new SplitMainSenderState; 386 pkt->senderState = main_send_state; --- 564 unchanged lines hidden --- |