timing.cc (10533:d1dce0b728b6) | timing.cc (10566:c99c8d2a7c31) |
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1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 257 unchanged lines hidden (view full) --- 266} 267 268void 269TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 270 bool read) 271{ 272 PacketPtr pkt; 273 buildPacket(pkt, req, read); | 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 257 unchanged lines hidden (view full) --- 266} 267 268void 269TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 270 bool read) 271{ 272 PacketPtr pkt; 273 buildPacket(pkt, req, read); |
274 pkt->dataDynamicArray<uint8_t>(data); | 274 pkt->dataDynamic |
275 if (req->getFlags().isSet(Request::NO_ACCESS)) { 276 assert(!dcache_pkt); 277 pkt->makeResponse(); 278 completeDataAccess(pkt); 279 } else if (read) { 280 handleReadPacket(pkt); 281 } else { 282 bool do_access = true; // flag to suppress cache access --- 91 unchanged lines hidden (view full) --- 374 } 375 376 buildPacket(pkt1, req1, read); 377 buildPacket(pkt2, req2, read); 378 379 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 380 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 381 | 275 if (req->getFlags().isSet(Request::NO_ACCESS)) { 276 assert(!dcache_pkt); 277 pkt->makeResponse(); 278 completeDataAccess(pkt); 279 } else if (read) { 280 handleReadPacket(pkt); 281 } else { 282 bool do_access = true; // flag to suppress cache access --- 91 unchanged lines hidden (view full) --- 374 } 375 376 buildPacket(pkt1, req1, read); 377 buildPacket(pkt2, req2, read); 378 379 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); 380 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand()); 381 |
382 pkt->dataDynamicArray<uint8_t>(data); | 382 pkt->dataDynamic |
383 pkt1->dataStatic<uint8_t>(data); 384 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 385 386 SplitMainSenderState * main_send_state = new SplitMainSenderState; 387 pkt->senderState = main_send_state; 388 main_send_state->fragments[0] = pkt1; 389 main_send_state->fragments[1] = pkt2; 390 main_send_state->outstanding = 2; --- 561 unchanged lines hidden --- | 383 pkt1->dataStatic<uint8_t>(data); 384 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 385 386 SplitMainSenderState * main_send_state = new SplitMainSenderState; 387 pkt->senderState = main_send_state; 388 main_send_state->fragments[0] = pkt1; 389 main_send_state->fragments[1] = pkt2; 390 main_send_state->outstanding = 2; --- 561 unchanged lines hidden --- |