timing.cc (10529:05b5a6cf3521) timing.cc (10533:d1dce0b728b6)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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238 notIdleFraction = 0;
239 _status = Idle;
240}
241
242bool
243TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
244{
245 RequestPtr req = pkt->req;
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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238 notIdleFraction = 0;
239 _status = Idle;
240}
241
242bool
243TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
244{
245 RequestPtr req = pkt->req;
246
247 // We're about the issues a locked load, so tell the monitor
248 // to start caring about this address
249 if (pkt->isRead() && pkt->req->isLLSC()) {
250 TheISA::handleLockedRead(thread, pkt->req);
251 }
246 if (req->isMmappedIpr()) {
247 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
248 new IprEvent(pkt, this, clockEdge(delay));
249 _status = DcacheWaitResponse;
250 dcache_pkt = NULL;
251 } else if (!dcachePort.sendTimingReq(pkt)) {
252 _status = DcacheRetry;
253 dcache_pkt = pkt;

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787 if (fault == NoFault)
788 countInst();
789 else if (traceData) {
790 // If there was a fault, we shouldn't trace this instruction.
791 delete traceData;
792 traceData = NULL;
793 }
794
252 if (req->isMmappedIpr()) {
253 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
254 new IprEvent(pkt, this, clockEdge(delay));
255 _status = DcacheWaitResponse;
256 dcache_pkt = NULL;
257 } else if (!dcachePort.sendTimingReq(pkt)) {
258 _status = DcacheRetry;
259 dcache_pkt = pkt;

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793 if (fault == NoFault)
794 countInst();
795 else if (traceData) {
796 // If there was a fault, we shouldn't trace this instruction.
797 delete traceData;
798 traceData = NULL;
799 }
800
795 // the locked flag may be cleared on the response packet, so check
796 // pkt->req and not pkt to see if it was a load-locked
797 if (pkt->isRead() && pkt->req->isLLSC()) {
798 TheISA::handleLockedRead(thread, pkt->req);
799 }
800
801 delete pkt->req;
802 delete pkt;
803
804 postExecute();
805
806 advanceInst(fault);
807}
808

--- 143 unchanged lines hidden --- 		801 delete pkt->req;
802 delete pkt;
803
804 postExecute();
805
806 advanceInst(fault);
807}
808

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