timing.cc (10464:2a0fe8bca031) timing.cc (10529:05b5a6cf3521)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"
60
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"
60
61#include "debug/Mwait.hh"
62
61using namespace std;
62using namespace TheISA;
63
64void
65TimingSimpleCPU::init()
66{
67 BaseCPU::init();
68

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813 ppCycles->notify(delta);
814
815 previousCycle = curCycle();
816}
817
818void
819TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
820{
63using namespace std;
64using namespace TheISA;
65
66void
67TimingSimpleCPU::init()
68{
69 BaseCPU::init();
70

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815 ppCycles->notify(delta);
816
817 previousCycle = curCycle();
818}
819
820void
821TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
822{
823 // X86 ISA: Snooping an invalidation for monitor/mwait
824 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
825 cpu->wakeup();
826 }
821 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
822}
823
827 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
828}
829
830void
831TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
832{
833 // X86 ISA: Snooping an invalidation for monitor/mwait
834 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
835 cpu->wakeup();
836 }
837}
824
825bool
826TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
827{
828 // delay processing of returned data until next CPU clock edge
829 Tick next_tick = cpu->clockEdge();
830
831 if (next_tick == curTick()) {

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839bool
840TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
841{
842 // delay processing of returned data until next CPU clock edge
843 Tick next_tick = cpu->clockEdge();
844
845 if (next_tick == curTick()) {

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