timing.cc (10407:a9023811bf9e) timing.cc (10464:2a0fe8bca031)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173{
174 BaseSimpleCPU::switchOut();
175
176 assert(!fetchEvent.scheduled());
177 assert(_status == BaseSimpleCPU::Running || _status == Idle);
178 assert(!stayAtPC);
179 assert(microPC() == 0);
180
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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173{
174 BaseSimpleCPU::switchOut();
175
176 assert(!fetchEvent.scheduled());
177 assert(_status == BaseSimpleCPU::Running || _status == Idle);
178 assert(!stayAtPC);
179 assert(microPC() == 0);
180
181 numCycles += curCycle() - previousCycle;
181 updateCycleCounts();
182}
183
184
185void
186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
187{
188 BaseSimpleCPU::takeOverFrom(oldCPU);
189

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327 }
328}
329
330void
331TimingSimpleCPU::translationFault(const Fault &fault)
332{
333 // fault may be NoFault in cases where a fault is suppressed,
334 // for instance prefetches.
182}
183
184
185void
186TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
187{
188 BaseSimpleCPU::takeOverFrom(oldCPU);
189

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327 }
328}
329
330void
331TimingSimpleCPU::translationFault(const Fault &fault)
332{
333 // fault may be NoFault in cases where a fault is suppressed,
334 // for instance prefetches.
335 numCycles += curCycle() - previousCycle;
336 previousCycle = curCycle();
335 updateCycleCounts();
337
338 if (traceData) {
339 // Since there was a fault, we shouldn't trace this instruction.
340 delete traceData;
341 traceData = NULL;
342 }
343
344 postExecute();

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564 setupFetchRequest(ifetch_req);
565 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
566 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
567 BaseTLB::Execute);
568 } else {
569 _status = IcacheWaitResponse;
570 completeIfetch(NULL);
571
336
337 if (traceData) {
338 // Since there was a fault, we shouldn't trace this instruction.
339 delete traceData;
340 traceData = NULL;
341 }
342
343 postExecute();

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563 setupFetchRequest(ifetch_req);
564 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
565 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
566 BaseTLB::Execute);
567 } else {
568 _status = IcacheWaitResponse;
569 completeIfetch(NULL);
570
572 numCycles += curCycle() - previousCycle;
573 previousCycle = curCycle();
571 updateCycleCounts();
574 }
575}
576
577
578void
579TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
580 ThreadContext *tc)
581{

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598 } else {
599 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
600 delete req;
601 // fetch fault: advance directly to next instruction (fault handler)
602 _status = BaseSimpleCPU::Running;
603 advanceInst(fault);
604 }
605
572 }
573}
574
575
576void
577TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
578 ThreadContext *tc)
579{

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596 } else {
597 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
598 delete req;
599 // fetch fault: advance directly to next instruction (fault handler)
600 _status = BaseSimpleCPU::Running;
601 advanceInst(fault);
602 }
603
606 numCycles += curCycle() - previousCycle;
607 previousCycle = curCycle();
604 updateCycleCounts();
608}
609
610
611void
612TimingSimpleCPU::advanceInst(const Fault &fault)
613{
614 if (_status == Faulting)
615 return;

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646
647 // received a response from the icache: execute the received
648 // instruction
649 assert(!pkt || !pkt->isError());
650 assert(_status == IcacheWaitResponse);
651
652 _status = BaseSimpleCPU::Running;
653
605}
606
607
608void
609TimingSimpleCPU::advanceInst(const Fault &fault)
610{
611 if (_status == Faulting)
612 return;

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643
644 // received a response from the icache: execute the received
645 // instruction
646 assert(!pkt || !pkt->isError());
647 assert(_status == IcacheWaitResponse);
648
649 _status = BaseSimpleCPU::Running;
650
654 numCycles += curCycle() - previousCycle;
655 previousCycle = curCycle();
651 updateCycleCounts();
656
657 if (pkt)
658 pkt->req->setAccessLatency();
659
660
661 preExecute();
662 if (curStaticInst && curStaticInst->isMemRef()) {
663 // load or store: just send to dcache

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748{
749 // received a response from the dcache: complete the load or store
750 // instruction
751 assert(!pkt->isError());
752 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
753 pkt->req->getFlags().isSet(Request::NO_ACCESS));
754
755 pkt->req->setAccessLatency();
652
653 if (pkt)
654 pkt->req->setAccessLatency();
655
656
657 preExecute();
658 if (curStaticInst && curStaticInst->isMemRef()) {
659 // load or store: just send to dcache

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744{
745 // received a response from the dcache: complete the load or store
746 // instruction
747 assert(!pkt->isError());
748 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
749 pkt->req->getFlags().isSet(Request::NO_ACCESS));
750
751 pkt->req->setAccessLatency();
756 numCycles += curCycle() - previousCycle;
757 previousCycle = curCycle();
758
752
753 updateCycleCounts();
754
759 if (pkt->senderState) {
760 SplitFragmentSenderState * send_state =
761 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
762 assert(send_state);
763 delete pkt->req;
764 delete pkt;
765 PacketPtr big_pkt = send_state->bigPkt;
766 delete send_state;

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804 delete pkt;
805
806 postExecute();
807
808 advanceInst(fault);
809}
810
811void
755 if (pkt->senderState) {
756 SplitFragmentSenderState * send_state =
757 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
758 assert(send_state);
759 delete pkt->req;
760 delete pkt;
761 PacketPtr big_pkt = send_state->bigPkt;
762 delete send_state;

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800 delete pkt;
801
802 postExecute();
803
804 advanceInst(fault);
805}
806
807void
808TimingSimpleCPU::updateCycleCounts()
809{
810 const Cycles delta(curCycle() - previousCycle);
811
812 numCycles += delta;
813 ppCycles->notify(delta);
814
815 previousCycle = curCycle();
816}
817
818void
812TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
813{
814 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
815}
816
817
818bool
819TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)

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820{
821 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
822}
823
824
825bool
826TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)

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