timing.cc (10342:711eb0e64249) timing.cc (10379:c00f6d7e2681)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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323 if (handleWritePacket()) {
324 send_state->clearFromParent();
325 }
326 }
327 }
328}
329
330void
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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323 if (handleWritePacket()) {
324 send_state->clearFromParent();
325 }
326 }
327 }
328}
329
330void
331TimingSimpleCPU::translationFault(Fault fault)
331TimingSimpleCPU::translationFault(const Fault &fault)
332{
333 // fault may be NoFault in cases where a fault is suppressed,
334 // for instance prefetches.
335 numCycles += curCycle() - previousCycle;
336 previousCycle = curCycle();
337
338 if (traceData) {
339 // Since there was a fault, we shouldn't trace this instruction.

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571
572 numCycles += curCycle() - previousCycle;
573 previousCycle = curCycle();
574 }
575}
576
577
578void
332{
333 // fault may be NoFault in cases where a fault is suppressed,
334 // for instance prefetches.
335 numCycles += curCycle() - previousCycle;
336 previousCycle = curCycle();
337
338 if (traceData) {
339 // Since there was a fault, we shouldn't trace this instruction.

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571
572 numCycles += curCycle() - previousCycle;
573 previousCycle = curCycle();
574 }
575}
576
577
578void
579TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
579TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
580 ThreadContext *tc)
580{
581 if (fault == NoFault) {
582 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
583 req->getVaddr(), req->getPaddr());
584 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
585 ifetch_pkt->dataStatic(&inst);
586 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
587

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603 }
604
605 numCycles += curCycle() - previousCycle;
606 previousCycle = curCycle();
607}
608
609
610void
581{
582 if (fault == NoFault) {
583 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
584 req->getVaddr(), req->getPaddr());
585 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
586 ifetch_pkt->dataStatic(&inst);
587 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
588

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604 }
605
606 numCycles += curCycle() - previousCycle;
607 previousCycle = curCycle();
608}
609
610
611void
611TimingSimpleCPU::advanceInst(Fault fault)
612TimingSimpleCPU::advanceInst(const Fault &fault)
612{
613 if (_status == Faulting)
614 return;
615
616 if (fault != NoFault) {
617 advancePC(fault);
618 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
619 reschedule(fetchEvent, clockEdge(), true);

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614 if (_status == Faulting)
615 return;
616
617 if (fault != NoFault) {
618 advancePC(fault);
619 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
620 reschedule(fetchEvent, clockEdge(), true);

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