timing.cc (10031:79d034cd6ba3) timing.cc (10342:711eb0e64249)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 335 unchanged lines hidden (view full) ---

344 postExecute();
345
346 advanceInst(fault);
347}
348
349void
350TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
351{
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 335 unchanged lines hidden (view full) ---

344 postExecute();
345
346 advanceInst(fault);
347}
348
349void
350TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
351{
352 MemCmd cmd;
353 if (read) {
354 cmd = MemCmd::ReadReq;
355 if (req->isLLSC())
356 cmd = MemCmd::LoadLockedReq;
357 } else {
358 cmd = MemCmd::WriteReq;
359 if (req->isLLSC()) {
360 cmd = MemCmd::StoreCondReq;
361 } else if (req->isSwap()) {
362 cmd = MemCmd::SwapReq;
363 }
364 }
365 pkt = new Packet(req, cmd);
352 pkt = read ? Packet::createRead(req) : Packet::createWrite(req);
366}
367
368void
369TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
370 RequestPtr req1, RequestPtr req2, RequestPtr req,
371 uint8_t *data, bool read)
372{
373 pkt1 = pkt2 = NULL;

--- 569 unchanged lines hidden --- 		353}
354
355void
356TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
357 RequestPtr req1, RequestPtr req2, RequestPtr req,
358 uint8_t *data, bool read)
359{
360 pkt1 = pkt2 = NULL;

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