timing.cc (10024:fc10e1f9f124) timing.cc (10030:b531e328342d)
1/*
1/*
2 * Copyright (c) 2010-2012 ARM Limited
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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91 fetchEvent(this), drainManager(NULL)
92{
93 _status = Idle;
94
95 system->totalNumInsts = 0;
96}
97
98
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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91 fetchEvent(this), drainManager(NULL)
92{
93 _status = Idle;
94
95 system->totalNumInsts = 0;
96}
97
98
99
99TimingSimpleCPU::~TimingSimpleCPU()
100{
101}
102
103unsigned int
104TimingSimpleCPU::drain(DrainManager *drain_manager)
105{
106 assert(!drainManager);

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268 pkt->makeResponse();
269 completeDataAccess(pkt);
270 } else if (read) {
271 handleReadPacket(pkt);
272 } else {
273 bool do_access = true; // flag to suppress cache access
274
275 if (req->isLLSC()) {
100TimingSimpleCPU::~TimingSimpleCPU()
101{
102}
103
104unsigned int
105TimingSimpleCPU::drain(DrainManager *drain_manager)
106{
107 assert(!drainManager);

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269 pkt->makeResponse();
270 completeDataAccess(pkt);
271 } else if (read) {
272 handleReadPacket(pkt);
273 } else {
274 bool do_access = true; // flag to suppress cache access
275
276 if (req->isLLSC()) {
276 do_access = TheISA::handleLockedWrite(thread, req);
277 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
277 } else if (req->isCondSwap()) {
278 assert(res);
279 req->setExtraData(*res);
280 }
281
282 if (do_access) {
283 dcache_pkt = pkt;
284 handleWritePacket();

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808 delete pkt->req;
809 delete pkt;
810
811 postExecute();
812
813 advanceInst(fault);
814}
815
278 } else if (req->isCondSwap()) {
279 assert(res);
280 req->setExtraData(*res);
281 }
282
283 if (do_access) {
284 dcache_pkt = pkt;
285 handleWritePacket();

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809 delete pkt->req;
810 delete pkt;
811
812 postExecute();
813
814 advanceInst(fault);
815}
816
817void
818TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
819{
820 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
821}
822
823
816bool
817TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
818{
819 // delay processing of returned data until next CPU clock edge
820 Tick next_tick = cpu->clockEdge();
821
822 if (next_tick == curTick()) {
823 cpu->completeDataAccess(pkt);

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825TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
826{
827 // delay processing of returned data until next CPU clock edge
828 Tick next_tick = cpu->clockEdge();
829
830 if (next_tick == curTick()) {
831 cpu->completeDataAccess(pkt);

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