timing.cc (10020:2f33cb012383) timing.cc (10024:fc10e1f9f124)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 401 unchanged lines hidden (view full) ---

410
411 if (traceData) {
412 traceData->setAddr(addr);
413 }
414
415 RequestPtr req = new Request(asid, addr, size,
416 flags, dataMasterId(), pc, _cpuId, tid);
417
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 401 unchanged lines hidden (view full) ---

410
411 if (traceData) {
412 traceData->setAddr(addr);
413 }
414
415 RequestPtr req = new Request(asid, addr, size,
416 flags, dataMasterId(), pc, _cpuId, tid);
417
418 req->taskId(taskId());
419
418 Addr split_addr = roundDown(addr + size - 1, block_size);
419 assert(split_addr <= addr || split_addr - addr < block_size);
420
421 _status = DTBWaitResponse;
422 if (split_addr > addr) {
423 RequestPtr req1, req2;
424 assert(!req->isLLSC() && !req->isSwap());
425 req->splitOnVaddr(split_addr, req1, req2);

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479
480 if (traceData) {
481 traceData->setAddr(addr);
482 }
483
484 RequestPtr req = new Request(asid, addr, size,
485 flags, dataMasterId(), pc, _cpuId, tid);
486
420 Addr split_addr = roundDown(addr + size - 1, block_size);
421 assert(split_addr <= addr || split_addr - addr < block_size);
422
423 _status = DTBWaitResponse;
424 if (split_addr > addr) {
425 RequestPtr req1, req2;
426 assert(!req->isLLSC() && !req->isSwap());
427 req->splitOnVaddr(split_addr, req1, req2);

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481
482 if (traceData) {
483 traceData->setAddr(addr);
484 }
485
486 RequestPtr req = new Request(asid, addr, size,
487 flags, dataMasterId(), pc, _cpuId, tid);
488
489 req->taskId(taskId());
490
487 Addr split_addr = roundDown(addr + size - 1, block_size);
488 assert(split_addr <= addr || split_addr - addr < block_size);
489
490 _status = DTBWaitResponse;
491 if (split_addr > addr) {
492 RequestPtr req1, req2;
493 assert(!req->isLLSC() && !req->isSwap());
494 req->splitOnVaddr(split_addr, req1, req2);

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556 return;
557
558 TheISA::PCState pcState = thread->pcState();
559 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
560
561 if (needToFetch) {
562 _status = BaseSimpleCPU::Running;
563 Request *ifetch_req = new Request();
491 Addr split_addr = roundDown(addr + size - 1, block_size);
492 assert(split_addr <= addr || split_addr - addr < block_size);
493
494 _status = DTBWaitResponse;
495 if (split_addr > addr) {
496 RequestPtr req1, req2;
497 assert(!req->isLLSC() && !req->isSwap());
498 req->splitOnVaddr(split_addr, req1, req2);

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560 return;
561
562 TheISA::PCState pcState = thread->pcState();
563 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
564
565 if (needToFetch) {
566 _status = BaseSimpleCPU::Running;
567 Request *ifetch_req = new Request();
568 ifetch_req->taskId(taskId());
564 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
565 setupFetchRequest(ifetch_req);
566 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
567 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
568 BaseTLB::Execute);
569 } else {
570 _status = IcacheWaitResponse;
571 completeIfetch(NULL);

--- 352 unchanged lines hidden --- 		569 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
570 setupFetchRequest(ifetch_req);
571 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
572 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
573 BaseTLB::Execute);
574 } else {
575 _status = IcacheWaitResponse;
576 completeIfetch(NULL);

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