1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/timing.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/TimingSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45Port *
46TimingSimpleCPU::getPort(const std::string &if_name, int idx)
47{
48 if (if_name == "dcache_port")
49 return &dcachePort;
50 else if (if_name == "icache_port")
51 return &icachePort;
52 else
53 panic("No Such Port\n");
54}
55
56void
57TimingSimpleCPU::init()
58{
59 BaseCPU::init();
60 cpuId = tc->readCpuId();
60#if FULL_SYSTEM
61 for (int i = 0; i < threadContexts.size(); ++i) {
62 ThreadContext *tc = threadContexts[i];
63
64 // initialize CPU, including PC
66 TheISA::initCPU(tc, cpuId);
65 TheISA::initCPU(tc, _cpuId);
66 }
67#endif
68}
69
70Tick
71TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
72{
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
74 return curTick;
75}
76
77void
78TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
79{
80 //No internal storage to update, jusst return
81 return;
82}
83
84void
85TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
86{
87 if (status == RangeChange) {
88 if (!snoopRangeSent) {
89 snoopRangeSent = true;
90 sendStatusChange(Port::RangeChange);
91 }
92 return;
93 }
94
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
96}
97
98
99void
100TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
101{
102 pkt = _pkt;
103 cpu->schedule(this, t);
104}
105
106TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
107 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this)
108{
109 _status = Idle;
110
111 icachePort.snoopRangeSent = false;
112 dcachePort.snoopRangeSent = false;
113
114 ifetch_pkt = dcache_pkt = NULL;
115 drainEvent = NULL;
116 previousTick = 0;
117 changeState(SimObject::Running);
118}
119
120
121TimingSimpleCPU::~TimingSimpleCPU()
122{
123}
124
125void
126TimingSimpleCPU::serialize(ostream &os)
127{
128 SimObject::State so_state = SimObject::getState();
129 SERIALIZE_ENUM(so_state);
130 BaseSimpleCPU::serialize(os);
131}
132
133void
134TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
135{
136 SimObject::State so_state;
137 UNSERIALIZE_ENUM(so_state);
138 BaseSimpleCPU::unserialize(cp, section);
139}
140
141unsigned int
142TimingSimpleCPU::drain(Event *drain_event)
143{
144 // TimingSimpleCPU is ready to drain if it's not waiting for
145 // an access to complete.
146 if (_status == Idle || _status == Running || _status == SwitchedOut) {
147 changeState(SimObject::Drained);
148 return 0;
149 } else {
150 changeState(SimObject::Draining);
151 drainEvent = drain_event;
152 return 1;
153 }
154}
155
156void
157TimingSimpleCPU::resume()
158{
159 DPRINTF(SimpleCPU, "Resume\n");
160 if (_status != SwitchedOut && _status != Idle) {
161 assert(system->getMemoryMode() == Enums::timing);
162
163 if (fetchEvent.scheduled())
164 deschedule(fetchEvent);
165
166 schedule(fetchEvent, nextCycle());
167 }
168
169 changeState(SimObject::Running);
170}
171
172void
173TimingSimpleCPU::switchOut()
174{
175 assert(_status == Running || _status == Idle);
176 _status = SwitchedOut;
177 numCycles += tickToCycles(curTick - previousTick);
178
179 // If we've been scheduled to resume but are then told to switch out,
180 // we'll need to cancel it.
181 if (fetchEvent.scheduled())
182 deschedule(fetchEvent);
183}
184
185
186void
187TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
188{
189 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
190
191 // if any of this CPU's ThreadContexts are active, mark the CPU as
192 // running and schedule its tick event.
193 for (int i = 0; i < threadContexts.size(); ++i) {
194 ThreadContext *tc = threadContexts[i];
195 if (tc->status() == ThreadContext::Active && _status != Running) {
196 _status = Running;
197 break;
198 }
199 }
200
201 if (_status != Running) {
202 _status = Idle;
203 }
204 assert(threadContexts.size() == 1);
206 cpuId = tc->readCpuId();
205 _cpuId = tc->cpuId();
206 previousTick = curTick;
207}
208
209
210void
211TimingSimpleCPU::activateContext(int thread_num, int delay)
212{
213 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
214
215 assert(thread_num == 0);
216 assert(thread);
217
218 assert(_status == Idle);
219
220 notIdleFraction++;
221 _status = Running;
222
223 // kick things off by initiating the fetch of the next instruction
224 schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
225}
226
227
228void
229TimingSimpleCPU::suspendContext(int thread_num)
230{
231 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
232
233 assert(thread_num == 0);
234 assert(thread);
235
236 assert(_status == Running);
237
238 // just change status to Idle... if status != Running,
239 // completeInst() will not initiate fetch of next instruction.
240
241 notIdleFraction--;
242 _status = Idle;
243}
244
245
246template <class T>
247Fault
248TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
249{
250 Request *req =
251 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
253 cpuId, /* thread ID */ 0);
252 _cpuId, /* thread ID */ 0);
253
254 if (traceData) {
255 traceData->setAddr(req->getVaddr());
256 }
257
258 // translate to physical address
259 Fault fault = thread->translateDataReadReq(req);
260
261 // Now do the access.
262 if (fault == NoFault) {
263 PacketPtr pkt =
264 new Packet(req,
265 (req->isLocked() ?
266 MemCmd::LoadLockedReq : MemCmd::ReadReq),
267 Packet::Broadcast);
268 pkt->dataDynamic<T>(new T);
269
270 if (req->isMmapedIpr()) {
271 Tick delay;
272 delay = TheISA::handleIprRead(thread->getTC(), pkt);
273 new IprEvent(pkt, this, nextCycle(curTick + delay));
274 _status = DcacheWaitResponse;
275 dcache_pkt = NULL;
276 } else if (!dcachePort.sendTiming(pkt)) {
277 _status = DcacheRetry;
278 dcache_pkt = pkt;
279 } else {
280 _status = DcacheWaitResponse;
281 // memory system takes ownership of packet
282 dcache_pkt = NULL;
283 }
284
285 // This will need a new way to tell if it has a dcache attached.
286 if (req->isUncacheable())
287 recordEvent("Uncached Read");
288 } else {
289 delete req;
290 }
291
292 if (traceData) {
293 traceData->setData(data);
294 }
295 return fault;
296}
297
298Fault
299TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
300 int size, unsigned flags)
301{
302 Request *req =
304 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
303 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
304
305 if (traceData) {
306 traceData->setAddr(vaddr);
307 }
308
309 Fault fault = thread->translateDataWriteReq(req);
310
311 if (fault == NoFault)
312 paddr = req->getPaddr();
313
314 delete req;
315 return fault;
316}
317
318#ifndef DOXYGEN_SHOULD_SKIP_THIS
319
320template
321Fault
322TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
323
324template
325Fault
326TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
327
328template
329Fault
330TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
331
332template
333Fault
334TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
335
336template
337Fault
338TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
339
340template
341Fault
342TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
343
344#endif //DOXYGEN_SHOULD_SKIP_THIS
345
346template<>
347Fault
348TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
349{
350 return read(addr, *(uint64_t*)&data, flags);
351}
352
353template<>
354Fault
355TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
356{
357 return read(addr, *(uint32_t*)&data, flags);
358}
359
360
361template<>
362Fault
363TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
364{
365 return read(addr, (uint32_t&)data, flags);
366}
367
368
369template <class T>
370Fault
371TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
372{
373 Request *req =
374 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
376 cpuId, /* thread ID */ 0);
375 _cpuId, /* thread ID */ 0);
376
377 if (traceData) {
378 traceData->setAddr(req->getVaddr());
379 }
380
381 // translate to physical address
382 Fault fault = thread->translateDataWriteReq(req);
383
384 // Now do the access.
385 if (fault == NoFault) {
386 MemCmd cmd = MemCmd::WriteReq; // default
387 bool do_access = true; // flag to suppress cache access
388
389 if (req->isLocked()) {
390 cmd = MemCmd::StoreCondReq;
391 do_access = TheISA::handleLockedWrite(thread, req);
392 } else if (req->isSwap()) {
393 cmd = MemCmd::SwapReq;
394 if (req->isCondSwap()) {
395 assert(res);
396 req->setExtraData(*res);
397 }
398 }
399
400 // Note: need to allocate dcache_pkt even if do_access is
401 // false, as it's used unconditionally to call completeAcc().
402 assert(dcache_pkt == NULL);
403 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
404 dcache_pkt->allocate();
405 dcache_pkt->set(data);
406
407 if (do_access) {
408 if (req->isMmapedIpr()) {
409 Tick delay;
410 dcache_pkt->set(htog(data));
411 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
412 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
413 _status = DcacheWaitResponse;
414 dcache_pkt = NULL;
415 } else if (!dcachePort.sendTiming(dcache_pkt)) {
416 _status = DcacheRetry;
417 } else {
418 _status = DcacheWaitResponse;
419 // memory system takes ownership of packet
420 dcache_pkt = NULL;
421 }
422 }
423 // This will need a new way to tell if it's hooked up to a cache or not.
424 if (req->isUncacheable())
425 recordEvent("Uncached Write");
426 } else {
427 delete req;
428 }
429
430 if (traceData) {
431 traceData->setData(data);
432 }
433
434 // If the write needs to have a fault on the access, consider calling
435 // changeStatus() and changing it to "bad addr write" or something.
436 return fault;
437}
438
439Fault
440TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
441 int size, unsigned flags)
442{
443 Request *req =
445 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
444 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
445
446 if (traceData) {
447 traceData->setAddr(vaddr);
448 }
449
450 Fault fault = thread->translateDataWriteReq(req);
451
452 if (fault == NoFault)
453 paddr = req->getPaddr();
454
455 delete req;
456 return fault;
457}
458
459
460#ifndef DOXYGEN_SHOULD_SKIP_THIS
461template
462Fault
463TimingSimpleCPU::write(Twin32_t data, Addr addr,
464 unsigned flags, uint64_t *res);
465
466template
467Fault
468TimingSimpleCPU::write(Twin64_t data, Addr addr,
469 unsigned flags, uint64_t *res);
470
471template
472Fault
473TimingSimpleCPU::write(uint64_t data, Addr addr,
474 unsigned flags, uint64_t *res);
475
476template
477Fault
478TimingSimpleCPU::write(uint32_t data, Addr addr,
479 unsigned flags, uint64_t *res);
480
481template
482Fault
483TimingSimpleCPU::write(uint16_t data, Addr addr,
484 unsigned flags, uint64_t *res);
485
486template
487Fault
488TimingSimpleCPU::write(uint8_t data, Addr addr,
489 unsigned flags, uint64_t *res);
490
491#endif //DOXYGEN_SHOULD_SKIP_THIS
492
493template<>
494Fault
495TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
496{
497 return write(*(uint64_t*)&data, addr, flags, res);
498}
499
500template<>
501Fault
502TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
503{
504 return write(*(uint32_t*)&data, addr, flags, res);
505}
506
507
508template<>
509Fault
510TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
511{
512 return write((uint32_t)data, addr, flags, res);
513}
514
515
516void
517TimingSimpleCPU::fetch()
518{
519 DPRINTF(SimpleCPU, "Fetch\n");
520
521 if (!curStaticInst || !curStaticInst->isDelayedCommit())
522 checkForInterrupts();
523
524 checkPcEventQueue();
525
526 bool fromRom = isRomMicroPC(thread->readMicroPC());
527
528 if (!fromRom) {
529 Request *ifetch_req = new Request();
531 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
530 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
531 Fault fault = setupFetchRequest(ifetch_req);
532
533 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
534 ifetch_pkt->dataStatic(&inst);
535
536 if (fault == NoFault) {
537 if (!icachePort.sendTiming(ifetch_pkt)) {
538 // Need to wait for retry
539 _status = IcacheRetry;
540 } else {
541 // Need to wait for cache to respond
542 _status = IcacheWaitResponse;
543 // ownership of packet transferred to memory system
544 ifetch_pkt = NULL;
545 }
546 } else {
547 delete ifetch_req;
548 delete ifetch_pkt;
549 // fetch fault: advance directly to next instruction (fault handler)
550 advanceInst(fault);
551 }
552 } else {
553 _status = IcacheWaitResponse;
554 completeIfetch(NULL);
555 }
556
557 numCycles += tickToCycles(curTick - previousTick);
558 previousTick = curTick;
559}
560
561
562void
563TimingSimpleCPU::advanceInst(Fault fault)
564{
565 advancePC(fault);
566
567 if (_status == Running) {
568 // kick off fetch of next instruction... callback from icache
569 // response will cause that instruction to be executed,
570 // keeping the CPU running.
571 fetch();
572 }
573}
574
575
576void
577TimingSimpleCPU::completeIfetch(PacketPtr pkt)
578{
579 DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
580
581 // received a response from the icache: execute the received
582 // instruction
583
584 assert(!pkt || !pkt->isError());
585 assert(_status == IcacheWaitResponse);
586
587 _status = Running;
588
589 numCycles += tickToCycles(curTick - previousTick);
590 previousTick = curTick;
591
592 if (getState() == SimObject::Draining) {
593 if (pkt) {
594 delete pkt->req;
595 delete pkt;
596 }
597
598 completeDrain();
599 return;
600 }
601
602 preExecute();
603 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
604 // load or store: just send to dcache
605 Fault fault = curStaticInst->initiateAcc(this, traceData);
606 if (_status != Running) {
607 // instruction will complete in dcache response callback
608 assert(_status == DcacheWaitResponse || _status == DcacheRetry);
609 assert(fault == NoFault);
610 } else {
611 if (fault == NoFault) {
612 // Note that ARM can have NULL packets if the instruction gets
613 // squashed due to predication
614 // early fail on store conditional: complete now
615 assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
616
617 fault = curStaticInst->completeAcc(dcache_pkt, this,
618 traceData);
619 if (dcache_pkt != NULL)
620 {
621 delete dcache_pkt->req;
622 delete dcache_pkt;
623 dcache_pkt = NULL;
624 }
625
626 // keep an instruction count
627 if (fault == NoFault)
628 countInst();
629 } else if (traceData) {
630 // If there was a fault, we shouldn't trace this instruction.
631 delete traceData;
632 traceData = NULL;
633 }
634
635 postExecute();
636 // @todo remove me after debugging with legion done
637 if (curStaticInst && (!curStaticInst->isMicroop() ||
638 curStaticInst->isFirstMicroop()))
639 instCnt++;
640 advanceInst(fault);
641 }
642 } else {
643 // non-memory instruction: execute completely now
644 Fault fault = curStaticInst->execute(this, traceData);
645
646 // keep an instruction count
647 if (fault == NoFault)
648 countInst();
649 else if (traceData) {
650 // If there was a fault, we shouldn't trace this instruction.
651 delete traceData;
652 traceData = NULL;
653 }
654
655 postExecute();
656 // @todo remove me after debugging with legion done
657 if (curStaticInst && (!curStaticInst->isMicroop() ||
658 curStaticInst->isFirstMicroop()))
659 instCnt++;
660 advanceInst(fault);
661 }
662
663 if (pkt) {
664 delete pkt->req;
665 delete pkt;
666 }
667}
668
669void
670TimingSimpleCPU::IcachePort::ITickEvent::process()
671{
672 cpu->completeIfetch(pkt);
673}
674
675bool
676TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
677{
678 if (pkt->isResponse() && !pkt->wasNacked()) {
679 // delay processing of returned data until next CPU clock edge
680 Tick next_tick = cpu->nextCycle(curTick);
681
682 if (next_tick == curTick)
683 cpu->completeIfetch(pkt);
684 else
685 tickEvent.schedule(pkt, next_tick);
686
687 return true;
688 }
689 else if (pkt->wasNacked()) {
690 assert(cpu->_status == IcacheWaitResponse);
691 pkt->reinitNacked();
692 if (!sendTiming(pkt)) {
693 cpu->_status = IcacheRetry;
694 cpu->ifetch_pkt = pkt;
695 }
696 }
697 //Snooping a Coherence Request, do nothing
698 return true;
699}
700
701void
702TimingSimpleCPU::IcachePort::recvRetry()
703{
704 // we shouldn't get a retry unless we have a packet that we're
705 // waiting to transmit
706 assert(cpu->ifetch_pkt != NULL);
707 assert(cpu->_status == IcacheRetry);
708 PacketPtr tmp = cpu->ifetch_pkt;
709 if (sendTiming(tmp)) {
710 cpu->_status = IcacheWaitResponse;
711 cpu->ifetch_pkt = NULL;
712 }
713}
714
715void
716TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
717{
718 // received a response from the dcache: complete the load or store
719 // instruction
720 assert(!pkt->isError());
721 assert(_status == DcacheWaitResponse);
722 _status = Running;
723
724 numCycles += tickToCycles(curTick - previousTick);
725 previousTick = curTick;
726
727 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
728
729 // keep an instruction count
730 if (fault == NoFault)
731 countInst();
732 else if (traceData) {
733 // If there was a fault, we shouldn't trace this instruction.
734 delete traceData;
735 traceData = NULL;
736 }
737
738 // the locked flag may be cleared on the response packet, so check
739 // pkt->req and not pkt to see if it was a load-locked
740 if (pkt->isRead() && pkt->req->isLocked()) {
741 TheISA::handleLockedRead(thread, pkt->req);
742 }
743
744 delete pkt->req;
745 delete pkt;
746
747 postExecute();
748
749 if (getState() == SimObject::Draining) {
750 advancePC(fault);
751 completeDrain();
752
753 return;
754 }
755
756 advanceInst(fault);
757}
758
759
760void
761TimingSimpleCPU::completeDrain()
762{
763 DPRINTF(Config, "Done draining\n");
764 changeState(SimObject::Drained);
765 drainEvent->process();
766}
767
768void
769TimingSimpleCPU::DcachePort::setPeer(Port *port)
770{
771 Port::setPeer(port);
772
773#if FULL_SYSTEM
774 // Update the ThreadContext's memory ports (Functional/Virtual
775 // Ports)
776 cpu->tcBase()->connectMemPorts(cpu->tcBase());
777#endif
778}
779
780bool
781TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
782{
783 if (pkt->isResponse() && !pkt->wasNacked()) {
784 // delay processing of returned data until next CPU clock edge
785 Tick next_tick = cpu->nextCycle(curTick);
786
787 if (next_tick == curTick)
788 cpu->completeDataAccess(pkt);
789 else
790 tickEvent.schedule(pkt, next_tick);
791
792 return true;
793 }
794 else if (pkt->wasNacked()) {
795 assert(cpu->_status == DcacheWaitResponse);
796 pkt->reinitNacked();
797 if (!sendTiming(pkt)) {
798 cpu->_status = DcacheRetry;
799 cpu->dcache_pkt = pkt;
800 }
801 }
802 //Snooping a Coherence Request, do nothing
803 return true;
804}
805
806void
807TimingSimpleCPU::DcachePort::DTickEvent::process()
808{
809 cpu->completeDataAccess(pkt);
810}
811
812void
813TimingSimpleCPU::DcachePort::recvRetry()
814{
815 // we shouldn't get a retry unless we have a packet that we're
816 // waiting to transmit
817 assert(cpu->dcache_pkt != NULL);
818 assert(cpu->_status == DcacheRetry);
819 PacketPtr tmp = cpu->dcache_pkt;
820 if (sendTiming(tmp)) {
821 cpu->_status = DcacheWaitResponse;
822 // memory system takes ownership of packet
823 cpu->dcache_pkt = NULL;
824 }
825}
826
827TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
828 Tick t)
829 : pkt(_pkt), cpu(_cpu)
830{
831 cpu->schedule(this, t);
832}
833
834void
835TimingSimpleCPU::IprEvent::process()
836{
837 cpu->completeDataAccess(pkt);
838}
839
840const char *
841TimingSimpleCPU::IprEvent::description() const
842{
843 return "Timing Simple CPU Delay IPR event";
844}
845
846
847void
848TimingSimpleCPU::printAddr(Addr a)
849{
850 dcachePort.printAddr(a);
851}
852
853
854////////////////////////////////////////////////////////////////////////
855//
856// TimingSimpleCPU Simulation Object
857//
858TimingSimpleCPU *
859TimingSimpleCPUParams::create()
860{
861 numThreads = 1;
862#if !FULL_SYSTEM
863 if (workload.size() != 1)
864 panic("only one workload allowed");
865#endif
866 return new TimingSimpleCPU(this);
867}