1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 129 unchanged lines hidden (view full) --- 138 139 assert(!threadContexts.empty()); 140 if (threadContexts.size() > 1) 141 fatal("The timing CPU only supports one thread.\n"); 142 143 if (thread->status() == ThreadContext::Active) { 144 schedule(fetchEvent, nextCycle()); 145 _status = BaseSimpleCPU::Running; |
146 notIdleFraction = 1; |
147 } else { 148 _status = BaseSimpleCPU::Idle; |
149 notIdleFraction = 0; |
150 } 151} 152 153bool 154TimingSimpleCPU::tryCompleteDrain() 155{ 156 if (!drainManager) 157 return false; --- 45 unchanged lines hidden (view full) --- 203{ 204 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 205 206 assert(thread_num == 0); 207 assert(thread); 208 209 assert(_status == Idle); 210 |
211 notIdleFraction = 1; |
212 _status = BaseSimpleCPU::Running; 213 214 // kick things off by initiating the fetch of the next instruction 215 schedule(fetchEvent, clockEdge(delay)); 216} 217 218 219void --- 7 unchanged lines hidden (view full) --- 227 if (_status == Idle) 228 return; 229 230 assert(_status == BaseSimpleCPU::Running); 231 232 // just change status to Idle... if status != Running, 233 // completeInst() will not initiate fetch of next instruction. 234 |
235 notIdleFraction = 0; |
236 _status = Idle; 237} 238 239bool 240TimingSimpleCPU::handleReadPacket(PacketPtr pkt) 241{ 242 RequestPtr req = pkt->req; 243 if (req->isMmappedIpr()) { --- 676 unchanged lines hidden --- |