1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 95 unchanged lines hidden (view full) --- 104 105TimingSimpleCPU::~TimingSimpleCPU() 106{ 107} 108 109unsigned int 110TimingSimpleCPU::drain(DrainManager *drain_manager) 111{ |
112 assert(!drainManager); 113 if (switchedOut()) 114 return 0; 115 |
116 if (_status == Idle || |
117 (_status == BaseSimpleCPU::Running && isDrained())) { |
118 assert(!fetchEvent.scheduled()); 119 DPRINTF(Drain, "No need to drain.\n"); 120 return 0; 121 } else { 122 drainManager = drain_manager; 123 DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 124 125 // The fetch event can become descheduled if a drain didn't 126 // succeed on the first attempt. We need to reschedule it if 127 // the CPU is waiting for a microcode routine to complete. |
128 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) |
129 schedule(fetchEvent, nextCycle()); |
130 131 return 1; 132 } 133} 134 135void 136TimingSimpleCPU::drainResume() 137{ 138 assert(!fetchEvent.scheduled()); |
139 assert(!drainManager); 140 if (switchedOut()) 141 return; |
142 143 DPRINTF(SimpleCPU, "Resume\n"); |
144 if (system->getMemoryMode() != Enums::timing) { 145 fatal("The timing CPU requires the memory system to be in " 146 "'timing' mode.\n"); 147 } |
148 |
149 assert(!threadContexts.empty()); 150 if (threadContexts.size() > 1) 151 fatal("The timing CPU only supports one thread.\n"); 152 153 if (thread->status() == ThreadContext::Active) { |
154 schedule(fetchEvent, nextCycle()); |
155 _status = BaseSimpleCPU::Running; 156 } else { 157 _status = BaseSimpleCPU::Idle; |
158 } 159} 160 161bool 162TimingSimpleCPU::tryCompleteDrain() 163{ 164 if (!drainManager) 165 return false; --- 14 unchanged lines hidden (view full) --- 180{ 181 BaseSimpleCPU::switchOut(); 182 183 assert(!fetchEvent.scheduled()); 184 assert(_status == BaseSimpleCPU::Running || _status == Idle); 185 assert(!stayAtPC); 186 assert(microPC() == 0); 187 |
188 numCycles += curCycle() - previousCycle; 189} 190 191 192void 193TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 194{ 195 BaseSimpleCPU::takeOverFrom(oldCPU); 196 |
197 previousCycle = curCycle(); 198} 199 200 201void 202TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 203{ 204 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); --- 715 unchanged lines hidden --- |